A 0.83 pJ/b 52Gb/s PAM-4 baud-rate CDR with pattern-based phase detector for short-reach applications
With increasing demand for 50Gb/S+, transceivers, PAM-4 modulation has become
dominant over NRZ modulation 1–5, 7, and multiphase clocking is used to maximize data …
dominant over NRZ modulation 1–5, 7, and multiphase clocking is used to maximize data …
A 0.14-to-0.29-pJ/bit 14-GBaud/s trimodal (NRZ/PAM-4/PAM-8) half-rate bang-bang clock and data recovery (BBCDR) circuit in 28-nm CMOS
This paper reports a half-rate bang-bang clock and data recovery (BBCDR) circuit
supporting the trimodal (NRZ/PAM-4/PAM-8) operation. The observation of their crossover …
supporting the trimodal (NRZ/PAM-4/PAM-8) operation. The observation of their crossover …
A 48 Gb/s PAM-4 receiver with pre-cursor adjustable baud-rate phase detector in 40 nm CMOS
This article presents a 48-Gb/s four-level pulse amplitude modulation (PAM-4) receiver with
a Baud-rate clock and data recovery (CDR) suitable for multi-level signaling. By deriving the …
a Baud-rate clock and data recovery (CDR) suitable for multi-level signaling. By deriving the …
A 56-Gb/s PAM4 transceiver with false-lock-aware locking scheme for Mueller-Müller CDR
F Tachibana, HC Ngo, G Urakawa, T Toi… - … 2022-IEEE 48th …, 2022 - ieeexplore.ieee.org
This paper presents a 56-Gb/s PAM4 transceiver using an ADC-based RX with a false-lock-
aware locking scheme for Mueller-Müller (MM) CDR. After the false-lock-aware locking …
aware locking scheme for Mueller-Müller (MM) CDR. After the false-lock-aware locking …
A 2.5–32 Gb/s gen 5-PCIe receiver with multi-rate CDR engine and hybrid DFE
This brief presents a 2.5–32 Gb/s Gen 5-PCIe receiver with a multi-rate clock and data
recovery (CDR) engine and a hybrid decision feedback equalizer (DFE). The receiver for the …
recovery (CDR) engine and a hybrid decision feedback equalizer (DFE). The receiver for the …
A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10-and 100-m Distances
Free-space wireless optical communication (FSO), which adopts the wavelength division
multiplexing (WDM) technology, transmits and receives various data and wavelength …
multiplexing (WDM) technology, transmits and receives various data and wavelength …
Hybrid timing error detector for baud rate multilevel clock and data recovery
This paper proposes a hybrid phase detector for use in multilevel timing recovery systems.
The proposed approach suppresses errant zero-crossings associated with multilevel baud …
The proposed approach suppresses errant zero-crossings associated with multilevel baud …
A Sub-Baud-Rate Wireline Receiver With One-Tap DFE
YH Yang, TC Lee - IEEE Journal of Solid-State Circuits, 2024 - ieeexplore.ieee.org
A 30-Gb/s sub-baud-rate (SBR) wireline receiver consists of a continuous-time-linear
equalizer, a one-tap decision-feedback equalizer, and a clock and data recovery (CDR) …
equalizer, a one-tap decision-feedback equalizer, and a clock and data recovery (CDR) …
A 48 Gb/s PAM4 receiver with Baud-rate phase-detector for multi-level signal modulation in 40 nm CMOS
K Lee, W Jung, H Ju, J Lee… - 2021 IEEE Asian Solid …, 2021 - ieeexplore.ieee.org
Recently, a receiver (RX) is demanding a high bandwidth data rate. Multi-level signals such
as four-level pulse amplitude modulation (PAM-4) are more advantageous than two-level …
as four-level pulse amplitude modulation (PAM-4) are more advantageous than two-level …
[HTML][HTML] A Digital Bang-Bang Clock and Data Recovery Circuit Combined with ADC-Based Wireline Receiver
Y Gu, X Feng, R Chi, J Wu, Y Chen - Electronics, 2022 - mdpi.com
With the great increases in data transmission rate requirements, analog-to-digital converter
(ADC)-based wireline receivers have received more and more attention due to their flexible …
(ADC)-based wireline receivers have received more and more attention due to their flexible …