A suite of IEEE 1687 benchmark networks
The saturation of the IJTAG concept and its approval as the IEEE 1687 standard in 2014 has
generated a wave of research activities and created demand for a set of appropriate and …
generated a wave of research activities and created demand for a set of appropriate and …
Reconfigurable scan networks: Modeling, verification, and optimal pattern generation
Efficient access to on-chip instrumentation is a key requirement for post-silicon validation,
test, debug, bringup, and diagnosis. Reconfigurable scan networks, as proposed by, for …
test, debug, bringup, and diagnosis. Reconfigurable scan networks, as proposed by, for …
Access time minimization in IEEE 1687 networks
R Krenz-Baath, FG Zadegan… - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
IEEE 1687 enables flexible access to the embedded (on-chip) instruments that are needed
for post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board …
for post-silicon validation, debugging, wafer sort, package test, burn-in, printed circuit board …
Design, verification, and application of IEEE 1687
IEEE 1687 (IJTAG) has been developed to enable flexible and automated access to the
increasing number of embedded instruments in today's integrated circuits. These …
increasing number of embedded instruments in today's integrated circuits. These …
Access port protection for reconfigurable scan networks
Scan infrastructures based on IEEE Std. 1149.1 (JTAG), 1500 (SECT), and P1687 (IJTAG)
provide a cost-effective access mechanism for test, reconfiguration, and debugging …
provide a cost-effective access mechanism for test, reconfiguration, and debugging …
Securing access to reconfigurable scan networks
R Baranowski, MA Kochte… - 2013 22nd Asian Test …, 2013 - ieeexplore.ieee.org
The accessibility of on-chip embedded infrastructure for test, reconfiguration, and debug
poses a serious safety and security problem. Special care is required in the design and …
poses a serious safety and security problem. Special care is required in the design and …
Optimization-based test scheduling for IEEE 1687 multi-power domain networks using Boolean satisfiability
The IEEE 1687 Std. provides an efficient access methodology for embedded instruments in
complex system-on-a-chip designs by introducing reconfigurable scan networks. This …
complex system-on-a-chip designs by introducing reconfigurable scan networks. This …
Analysis and design of an on-chip retargeting engine for IEEE 1687 networks
A Ibrahim, HG Kerkhoff - 2016 21th IEEE European Test …, 2016 - ieeexplore.ieee.org
IEEE 1687 (iJTAG) standard introduces a methodology for accessing the increasing number
of embedded instruments found in modern System-on-Chips. Retargeting is defined by …
of embedded instruments found in modern System-on-Chips. Retargeting is defined by …
Power-aware test scheduling framework for IEEE 1687 multi-power domain networks using formal techniques
Abstract The IEEE 1687 Std.(IJTAG) introduces an efficient access methodology based on
reconfigurable scan networks to address the ever-increasing complexity of the latest system …
reconfigurable scan networks to address the ever-increasing complexity of the latest system …
Power-aware test scheduling for IEEE 1687 networks with multiple power domains
New test access methodologies are required to cope with the ever-increasing complexity of
latest system-on-a-chip designs. The IEEE 1687 standard defines an access methodology to …
latest system-on-a-chip designs. The IEEE 1687 standard defines an access methodology to …