Monolithic three dimensional integration of semiconductor integrated circuits
Y Du - US Patent 9,177,890, 2015 - Google Patents
(57) ABSTRACT A three-dimensional integrated circuit comprising top tier nanowire
transistors formed on a bottom tier of CMOS tran sistors, with inter-tier vias, intra-tier vias …
transistors formed on a bottom tier of CMOS tran sistors, with inter-tier vias, intra-tier vias …
3D floorplanning using 2D and 3D blocks
The disclosed embodiments are directed to systems and method for floorplanning an
integrated circuit design using a mix of 2D and 3D blocks that provide a significant …
integrated circuit design using a mix of 2D and 3D blocks that provide a significant …
Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods
Y Du - US Patent 9,536,840, 2017 - Google Patents
(57) ABSTRACT A three-dimensional (3-D) integrated circuit (3DIC) with a graphene shield
is disclosed. In certain embodiments, at least a graphene layer is positioned between two …
is disclosed. In certain embodiments, at least a graphene layer is positioned between two …
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related methods
Y Du, J Xie, K Samadi - US Patent 9,041,448, 2015 - Google Patents
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC)(3DIC) and related
method are disclosed. In one embodiment, a single clock source is provided for the 3DIC …
method are disclosed. In one embodiment, a single clock source is provided for the 3DIC …
Clock distribution network for 3D integrated circuit
5,724,557 A* 3/1998 McBean, Sr.................. T16, 113 2011/O121366 A1 5/2011 Or-Bach et
al. 6,040,203 A 3/2000 Bozso et al. 2011/0215300 A1 9, 2011 Guo et al. 6,125,217 A 9 …
al. 6,040,203 A 3/2000 Bozso et al. 2011/0215300 A1 9, 2011 Guo et al. 6,125,217 A 9 …
Wide-range many-core SoC design in scaled CMOS: Challenges and opportunities
The system-on-chip (SoC) designs for future Internet of Things (IoT) systems, spanning client
platforms to cloud datacenters, need to deliver uncompromising and scalable performance …
platforms to cloud datacenters, need to deliver uncompromising and scalable performance …
Single-ended 9T SRAM cell for near-threshold voltage operation with enhanced read performance in 22-nm FinFET technology
Y Yang, J Park, SC Song, J Wang… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Although near-threshold (Vth) operation is an attractive method for energy and performance-
constrained applications, it suffers from problems in terms of circuit stability, particularly, for …
constrained applications, it suffers from problems in terms of circuit stability, particularly, for …
Centip3De: A cluster-based NTC architecture with 64 ARM Cortex-M3 cores in 3D stacked 130 nm CMOS
We present Centip3De, a large-scale 3D CMP with a cluster-based near-threshold
computing (NTC) architecture. Centip3De uses a 3D stacking technology in conjunction with …
computing (NTC) architecture. Centip3De uses a 3D stacking technology in conjunction with …
NeuroSim V1. 4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node
Over the past decade, numerous compute-in-memory (CIM) platforms have been proposed
in the literature. While emerging non-volatile memory based analog CIM (ACIM) has been …
in the literature. While emerging non-volatile memory based analog CIM (ACIM) has been …
A 128 kb 7T SRAM using a single-cycle boosting mechanism in 28-nm FD–SOI
B Mohammadi, O Andersson, J Nguyen… - … on Circuits and …, 2017 - ieeexplore.ieee.org
A 128-kb ultra-low voltage SRAM, based on a leakage optimized single-WELL 7T bitcell in
28-nm FD-SOI technology is presented. An ideal power management scenario in a single …
28-nm FD-SOI technology is presented. An ideal power management scenario in a single …