This paper demonstrates the improved adaptation of the Vedic Multiplier using the Vedic
standards, which includes old sutras. In this paper, current and proposed model are …

Multiplication is a fundamental operation in most signal and image processing applications.
In this paper, a new architecture for a Vedic multiplier implementing 'Urdhava-tiryakbhyam' …

The proposed research work specifies the modified version of binary vedic multiplier using
vedic sutras of ancient vedic mathematics. It provides modification in prelimi-narilry …

In this paper, two novel methods to design a high speed, low power 16-Tap 32-bit digital FIR
filter for DSP application are proposed. The basic building blocks of the FIR filters are …

The most widely used operation in digital signal processing is Multiply and Accumulate
(MAC) unit. The area occupied by the MAC unit and the power consumed will largely affect …

The paper presents a new and modified area and power efficient carry select adder is
proposed using Weinberger architecture and it is compared for efficiency with modified …

In the work below we have formulated and examined 8-bit vedic multiplier using (RC) Ripple
carry adder,(CSL) Carry select adder,(CSl) Carry select adder using Binary to excess-1 …

Carry Select Adder is one of the important adders used for arithmetic operations. It is a high
speed adder used in VLSI architectures but at the expense of area and power. In this paper …

Floating-point arithmetic plays major role in computer systems. Many of the digital signal
processing applications use floating-point algorithms for execution of the floating-point …

Micro-processor designs have become a revolutionary technology almost in every industry.
They brought the reality of automation and also electronic gadgets. While trying to improvise …