Field-programmable gate arrays in a low power vision system

P Suresh, U Saravanakumar, C Iwendi, S Mohan… - Computers & Electrical …, 2021 - Elsevier
In recent years, field-programmable gate arrays have played a major role in developing low
power electronic systems. End users usually prefer systems with high performance, reduced …

Dynamic partial reconfiguration profitability for real-time systems

G Valente, T Di Mascio, L Pomante… - IEEE Embedded …, 2020 - ieeexplore.ieee.org
Modern field-programmable gate arrays offer dynamic partial reconfiguration (DPR)
capabilities, a characteristic that opens new scheduling opportunities for real-time …

Simple Adaptive Control‐Based Reconfiguration Design of Cabin Pressure Control System

Z Zhang, Z Yang, S Xiong, S Chen, S Liu… - Complexity, 2021 - Wiley Online Library
The Cabin Pressure Control System (CPCS) is an essential part of the aviation
environmental control system that ensures aircraft structure and flight crew safety. However …

A run-time reconfiguration method for an FPGA-based electrical capacitance tomography system

D Wanta, WT Smolik, J Kryszyn, P Wróblewski… - Electronics, 2022 - mdpi.com
A desirable feature of an electrical capacitance tomography system is the adaptation
possibility to any sensor configuration and measurement mode. A run-time reconfiguration of …

Recpe: A pe for reconfigurable lightweight cryptography

J Anderson, Y Alkabani… - 2021 IEEE 34th …, 2021 - ieeexplore.ieee.org
The Internet-of-Things has given rise to an over-whelming number of resource-constrained
devices which must communicate securely with a core server. Due to the variability in …

[PDF][PDF] Implementation of network traffic monitoring using software defined networking Ryu controller

O Alssaheli, Z Zainal Abidin, N Zakaria… - WSEAS Trans. Syst …, 2021 - wseas.com
Network traffic monitoring is vital for enhancing the overall network performance and for
optimizing the traffic flows. However, an emerging growth of use in cloud services, internet-of …

VR-ZYCAP: a versatile resourse-level ICAP controller for ZYNQ SOC

B Sultana, A Ullah, AA Malik, A Zahir, P Reviriego… - Electronics, 2021 - mdpi.com
Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for
example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several …

Intelligent optimization approaches for a secured dynamic partial reconfigurable architecture-based health monitoring system

RS Ram, MLC Prabhaker - Journal of Circuits, Systems and …, 2023 - World Scientific
In this work, an intelligent multi-objective optimization technique is proposed to optimize
various parameters such as power consumption (P c), computation time (C t) and area (A) …

Co-design of multicore hardware and multithreaded software for thread performance assessment on an FPGA

GK Adam - Computers, 2022 - mdpi.com
Multicore and multithreaded architectures increase the performance of computing systems.
The increase in cores and threads, however, raises further issues in the efficiency achieved …

A reconfigurable architecture to implement linear transforms of image processing applications

A Sanyal, A Sinha - Proceedings of International Conference on Frontiers …, 2021 - Springer
A reconfigurable architecture capable of implementing flow graph-based computationally
intensive image processing transforms is introduced. The conceptual design of the …