Design principles for lifelong learning AI accelerators
Lifelong learning—an agent's ability to learn throughout its lifetime—is a hallmark of
biological learning systems and a central challenge for artificial intelligence (AI). The …
biological learning systems and a central challenge for artificial intelligence (AI). The …
An electromagnetic perspective of artificial intelligence neuromorphic chips
The emergence of artificial intelligence has represented great potential in solving a wide
range of complex problems. However, traditional general-purpose chips based on von …
range of complex problems. However, traditional general-purpose chips based on von …
Diana: An end-to-end hybrid digital and analog neural network soc for the edge
DIgital-ANAlog (DIANA), a heterogeneous multi-core accelerator, combines a reduced
instruction set computer-five (RISC-V) host processor with an analog in-memory computing …
instruction set computer-five (RISC-V) host processor with an analog in-memory computing …
Accelerating large-scale graph neural network training on crossbar diet
Resistive random-access memory (ReRAM)-based manycore architectures enable
acceleration of graph neural network (GNN) inference and training. GNNs exhibit …
acceleration of graph neural network (GNN) inference and training. GNNs exhibit …
Memristor-based storage system with convolutional autoencoder-based image compression network
The exponential growth of various complex images is putting tremendous pressure on
storage systems. Here, we propose a memristor-based storage system with an integrated …
storage systems. Here, we propose a memristor-based storage system with an integrated …
Memristor-based hardware accelerators for artificial intelligence
Satisfying the rapid evolution of artificial intelligence (AI) algorithms requires exponential
growth in computing resources, which, in turn, presents huge challenges for deploying AI …
growth in computing resources, which, in turn, presents huge challenges for deploying AI …
Fusion of memristor and digital compute-in-memory processing for energy-efficient edge computing
Artificial intelligence (AI) edge devices prefer employing high-capacity nonvolatile compute-
in-memory (CIM) to achieve high energy efficiency and rapid wakeup-to-response with …
in-memory (CIM) to achieve high energy efficiency and rapid wakeup-to-response with …
A 28-nm 8-bit Floating-Point Tensor Core-Based Programmable CNN Training Processor With Dynamic Structured Sparsity
Training deep/convolutional neural networks (DNNs/CNNs) requires a large amount of
memory and iterative computation, which necessitates speedup and energy reduction …
memory and iterative computation, which necessitates speedup and energy reduction …
PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM
Recently, researchers have demonstrated multiple-bits-per-cell (MBPC) data storage using
resistive random access memory (RRAM) device technologies. In MBPC storage, a level …
resistive random access memory (RRAM) device technologies. In MBPC storage, a level …
RoboVisio: A Micro-Robot Vision Domain-Specific SoC for Autonomous Navigation Enabling Fully-on-Chip Intelligence via 2-MB eMRAM
This article presents RoboVisio, an efficient and highly flexible domain-specific system-on-
chip (SoC) for vision tasks in fully autonomous micro-robot navigation. A novel hybrid …
chip (SoC) for vision tasks in fully autonomous micro-robot navigation. A novel hybrid …