Much of the complexity and overhead (directory, state bits, invalidations) of a typical
directory coherence implementation stems from the effort to make it" invisible" even to the …

Abstract System and methods for cache coherence in a multi-core processing environment
having a local/shared cache hierarchy. The system includes multiple processor cores, a …

Designing massive scale cache coherence systems has been an elusive goal. Whether it be
on large-scale GPUs, future thousand-core chips, or across million-core warehouse scale …

Hierarchical clustered cache designs are becoming an appealing alternative for multicores.
Grouping cores and their caches in clusters reduces network congestion by localizing traffic …

Embedded devices are becoming more and more present everywhere. Moreover mobile
devices are becoming also more computationally powerful. These embedded architectures …

Data-intensive applications put immense strain on the memory systems of Graphics
Processing Units (GPUs). To cater to this need, GPU memory systems distribute requests …

Most of the data referenced by sequential and parallel applications running in current chip
multiprocessors are referenced by only one thread and can be considered as private data. A …

Last-level caches are increasingly distributed, consisting of many small banks. To perform
well, most accesses must be served by banks near requesting cores. An attractive approach …

Weak memory consistency models can maximize system performance by enabling
hardware and compiler optimizations, but increase programming complexity since they do …

Most of the data referenced by sequential and parallel applications running in current chip
multiprocessors are referenced by a single thread, ie, private. Recent proposals leverage …