Computer architects have been studying the dynamically reconfigurable computer
(Schaumont, Verbauwhede, Keutzer, and Sarrafzadeh,“A Quick Safari through the …

In this paper, we consider the scheduling of periodic real-time tasks on reconfigurable
hardware devices. Such devices can execute several tasks in parallel. All executing tasks …

When modern partially and dynamically reconfigurable FPGAs are to be used as resources
in hard real-time systems, the two dimensions area and time have to be considered in the …

DSP applications can be suitably represented using process network models. This paper
uses a modification of Kahn process network to solve the problem of finding an optimum …

Partial Reconfiguration is a common technique on FPGA platforms to load hardware
accelerators at runtime without interrupting the remaining system. One crucial element is the …

Processors that deploy reconfigurable fabrics to implement application-specific accelerators
on-demand obtained significant attention within the last decade. They trade-off the flexibility …

To conserve space and power as well as to harness high performance in embedded
systems, high utilization of the hardware is required. This can be facilitated through dynamic …

The partitioning of computing platforms is a wellknown technique for achieving fault isolation
and fault tolerance in space avionics. With the advent of large-capacity and partially …

Reconfigurable hardware devices, such as FPGAs, are increasingly used in embedded
systems. To utilize these devices for real-time work loads, scheduling techniques are …

Embedded smart cameras must provide enough computational power to handle complex
image understanding algorithms on huge amount of data in-situ. In a distributed set-up …