Design Approaches of Ultra-Low Power SAR ADC for Biomedical Systems—A Review

K Aneesh, G Manoj, S Shylu Sam - Journal of Circuits, Systems and …, 2022 - World Scientific
In recent years, implantable biomedical devices like cardiac pacemaker, defibrillators,
cochlear implants, visual prosthesis etc. have gained immense importance in the personal …

A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage

JK Folla, ML Crespo, ET Wembe… - IET Circuits, Devices …, 2021 - Wiley Online Library
The preamplifier module is a crucial element while designing dynamic latch comparators.
The traditional double tail comparator utilizes a differential pair as the preamplifier stage …

A bulk-driven quasi-floating gate FVF current mirror for low voltage, low power applications

M Bchir, I Aloui, N Hassen - Integration, 2020 - Elsevier
This paper introduces a new low-voltage, low-power FVF current mirror circuit. The bulk-
driven (BD) technique is employed to achieve extended input voltage swing and low supply …

Cascode cross-coupled stage high-speed dynamic comparator in 65 nm CMOS

K Krishna, N Nambath - IEEE Transactions on Very Large Scale …, 2023 - ieeexplore.ieee.org
Dynamic comparators are the core of high-speed, high-resolution analog-to-digital
converters (ADCs) used for communication applications. Most of the dynamic comparators …

A low offset low power CMOS dynamic comparator for analog to digital converters

Y Huijing, L Shichang, R Mingyuan - Integration, 2023 - Elsevier
In this research, a new architecture of dynamic latch comparator is presented, which is able
to provide high-speed, consumes low-power and low offset voltage. The proposed …

A novel framework of genetic algorithm and spectre to optimize delay and power consumption in designing dynamic comparators

HT Nguyen, T Hoang - Electronics, 2023 - mdpi.com
In integrated circuit (IC) design, analog circuits contribute significantly as the interface
between real and digital world signals. Although they make up a relatively small portion of …

A high‐speed and power efficient CMOS dynamic comparator for data converter circuits

K Brindha, J Manjula - International Journal of Numerical …, 2024 - Wiley Online Library
Complementary metal oxide semiconductor (CMOS) comparators play a pivotal role in
analog and mixed‐signal circuits, finding diverse applications across electronic systems. In …

Design and Investigation of the 22 nm FinFET Based Dynamic Latched Comparator for Low Power Applications

K Sarangam, AS Kumar, BNK Reddy - Transactions on Electrical and …, 2024 - Springer
A low-power, high-speed two-stage dynamic latch comparator suitable for high-resolution
analog-to-digital converters (ADCs) is described and implemented in this work using 22 nm …

Design and analysis of a high-speed low-power comparator with regeneration enhancement and through current suppression techniques from 4 K to 300 K in 65-nm …

CW Pai, K Uchida, M Tada, H Ishikuro - Microelectronics Journal, 2024 - Elsevier
This paper presents a high-speed low-power cryogenic CMOS two-stage dynamic
comparator for SAR ADC. The pre-amplifier uses the dynamic bias technique to save power …

A 0.67-to-5.4 TSOPs/W Spiking Neural Network Accelerator With 128/256 Reconfigurable Neurons and Asynchronous Fully Connected Synapses

X Qi, X Li, Y Lou, Y Li, G Wang… - IEEE Journal of Solid …, 2024 - ieeexplore.ieee.org
Spiking neural networks (SNNs) are garnering increasing attention due to their potential to
explore the complexities of the human brain and utilize its capabilities. The broad spectrum …