High speed vedic multiplier designs-A review

Y Bansal, C Madhu, P Kaur - 2014 Recent Advances in …, 2014 - ieeexplore.ieee.org
Multipliers are the key block in high speed arithmetic logic units, multiplier and accumulate
units, digital signal processing units etc. With the increasing constraints on delay, more and …

A novel high-speed approach for 16× 16 Vedic multiplication with compressor adders

Y Bansal, C Madhu - Computers & Electrical Engineering, 2016 - Elsevier
In this paper, a novel architecture of Vedic multiplier with 'Urdhava-tiryakbhyam'methodology
for 16 bit multiplier and multiplicand is proposed with the use of compressor adders …

Vedic mathematics for sustainable knowledge: a systematic literature review

A Kumar, VP Joshith - International Journal of Comparative Education …, 2024 - emerald.com
Purpose This research lies in the domain of Vedic mathematics, and it explores the
application of the related Vedic sutras in different branches of mathematics, science …

Design of efficient quantum Dot cellular automata (QCA) multiply accumulate (MAC) unit with power dissipation analysis

I Gassoumi, L Touil, B Ouni - IET Circuits, Devices & Systems, 2019 - Wiley Online Library
Quantum dot cellular automata (QCA) is a hopeful technology in the field of nanotechnology
that seems to suite well with signal‐processing needs. It is concerned with great interest …

High speed vedic multiplier used vedic mathematics

DKB Kahar, H Mehta - 2017 International Conference on …, 2017 - ieeexplore.ieee.org
Multiplier is main building block of all processor, which improves the speed of Digital Signal
Processor (DSP). In special application in which we need to reduce the time delay. In …

The application of non-volatile look-up-table operations based on multilevel-cell of resistance switching random access memory

F Zhang, DY Fan, QP Lin, Q Huo, Y Li… - … Symposium on VLSI …, 2018 - ieeexplore.ieee.org
Resistance switching random access memory (RRAM) is deemed as an emerging memory
which has drawn considerable attention. This paper presents an approach for the synthesis …

Low power multiplier architectures using Vedic mathematics in 45nm technology for high speed computing

S Tripathy, LB Omprakash, SK Mandal… - 2015 International …, 2015 - ieeexplore.ieee.org
Speed and the overall performance of any digital signal processor are largely determined by
the efficiency of the multiplier units present within. The use of Vedic mathematics has …

Comparison of a 32-bit Vedic multiplier with a conventional binary multiplier

A Bisoyi, M Baral, MK Senapati - 2014 IEEE International …, 2014 - ieeexplore.ieee.org
Binary multipliers and addresses are used in the design and development of Arithmetic
Logic Unit (ALU), Digital Signal Processing (DSP) Processors, Multiply and Accumulate …

Design and performance analysis of Multiply-Accumulate (MAC) unit

MS Kumar, DA Kumar… - … Conference on Circuits …, 2014 - ieeexplore.ieee.org
In recent years, Multiply-Accumulate (MAC) unit is developing for various high performance
applications. MAC unit is a fundamental block in the computing devices, especially Digital …

Design of speed, energy and power efficient reversible logic based vedic ALU for digital processors

A Gupta, U Malviya, V Kapse - 2012 Nirma University …, 2012 - ieeexplore.ieee.org
Now days most of the circuits which are going to be designed to perform any specific or
safety critical operations are mainly based upon the digital domain, where microprocessors …