Continuous downscaling of CMOS technology at the nanometer scale with conventional
MOSFETs leads to short channel effects (SCE), increased subthreshold slope (SS), and …

With FinFETs scaled below 20 nm technology nodes, nanodevices are not immune to Short
Channel Effects (SCEs) leading to reduced carrier mobility, transconductance and finally …

With the tremendous scaling of planar MOSFETs to keep abreast with Moore's law, the
performance of the MOSFET devices have degraded due to the Short Channel Effects. This …

Incubating strain technology in MOSFET arena with, combination of strained Si, strained
SiGe and relaxed SiGe forming a single or dual channel has been developed widely, while …

In order to improve the drive current and subthreshold swing (SS), a novel vertical-dual-
source tunneling field-effect transistor (VDSTFET) device is proposed in this paper. The …

Here we proposes and optimizes a delta doped dual spacer negative capacitance TFET to
improve ON current, steeper sub threshold slope, and ON to OFF current ratio. The inclusion …

Introducing three ultrathin-strained layers in the channel forming heterostructure-on-
insulator (HOI) cylindrical gate-all-around (CGAA) FET is the requisite at nano regime. The …

With continuous scaling of MOSFETs dimensions, the efficiency of the MOSFET devices
have deteriorated. Beyond 20 nm, scaling becomes even more challenging as FinFETs are …

In comparison with planar MOSFETs, multiple gate FETs such as trigate FinFETs are able to
be effectively scaled down beyond 32 nm technology, with increasing device performance …

Introducing three ultrathin-strained layers in the channel forming heterostructure-on-
insulator (HOI) cylindrical gate-all-around (CGAA) FET is the requisite at nano regime. The …