A survey of computer architecture simulation techniques and tools

A Akram, L Sawalha - Ieee Access, 2019 - ieeexplore.ieee.org
Computer architecture simulators play an important role in advancing computer architecture
research. With wider research directions and the increased number of simulators that have …

Graphite: A distributed parallel simulator for multicores

JE Miller, H Kasture, G Kurian… - HPCA-16 2010 The …, 2010 - ieeexplore.ieee.org
This paper introduces the Graphite open-source distributed parallel multicore simulator
infrastructure. Graphite is designed from the ground up for exploration of future multi-core …

The case for lifetime reliability-aware microprocessors

J Srinivasan, SV Adve, P Bose, JA Rivers - ACM SIGARCH Computer …, 2004 - dl.acm.org
Ensuring long processor lifetimes by limiting failuresdue to wear-out related hard errors is a
critical requirementfor all microprocessor manufacturers. We observethat continuous device …

Unbounded transactional memory

CS Ananian, K Asanovic, BC Kuszmaul… - … Symposium on High …, 2005 - ieeexplore.ieee.org
Hardware transactional memory should support unbounded transactions: transactions of
arbitrary size and duration. We describe a hardware implementation of unbounded …

ECOSystem: Managing energy as a first class operating system resource

H Zeng, CS Ellis, AR Lebeck, A Vahdat - ACM SIGOPS operating …, 2002 - dl.acm.org
Energy consumption has recently been widely recognized as a major challenge of computer
systems design. This paper explores how to support energy as a first-class operating system …

Stonne: Enabling cycle-level microarchitectural simulation for dnn inference accelerators

F Muñoz-Martínez, JL Abellán… - 2021 IEEE …, 2021 - ieeexplore.ieee.org
The design of specialized architectures for accelerating the inference procedure of Deep
Neural Networks (DNNs) is a booming area of research nowadays. While first-generation …

MinneSPEC: A new SPEC benchmark workload for simulation-based computer architecture research

AJ KleinOsowski, DJ Lilja - IEEE Computer Architecture Letters, 2002 - ieeexplore.ieee.org
Computer architects must determine how tomost effectively use finite computational
resources whenrunning simulations to evaluate new architectural ideas. To facilitate efficient …

Warped-slicer: Efficient intra-SM slicing through dynamic resource partitioning for GPU multiprogramming

Q Xu, H Jeon, K Kim, WW Ro… - ACM SIGARCH Computer …, 2016 - dl.acm.org
As technology scales, GPUs are forecasted to incorporate an ever-increasing amount of
computing resources to support thread-level parallelism. But even with the best effort …

A survey on cache tuning from a power/energy perspective

W Zang, A Gordon-Ross - ACM Computing Surveys (CSUR), 2013 - dl.acm.org
Low power and/or energy consumption is a requirement not only in embedded systems that
run on batteries or have limited cooling capabilities, but also in desktop and mainframes …

Mparm: Exploring the multi-processor soc design space with systemc

L Benini, D Bertozzi, A Bogliolo, F Menichelli… - Journal of VLSI signal …, 2005 - Springer
Technology is making the integration of a large number of processors on the same silicon
die technically feasible. These multi-processor systems-on-chip (MP-SoC) can provide a …