Resource-efficient RISC-V Vector Extension Architecture for FPGA-based Accelerators

GenVectorX: A performance-portable SYCL library for Lorentz Vectors operations

M Dessole, J Chen, A Naumann - arXiv preprint arXiv:2312.02756, 2023 - arxiv.org
The Large Hadron Collider (LHC) at CERN will see an upgraded hardware configuration
which will bring a new era of physics data taking and related computational challenges. To …
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[PDF][PDF] Vector Unit for Deeply-embedded, Low-power RISC-V Processors

ASS Allam - 2024 - ntnuopen.ntnu.no
Dagens smarte verden er avhengig av at små datamaskiner bygges inn i ulike produkter for
å forbedre folks liv. Disse dypt innebygde enhetene forventes i økende grad å gi høy ytelse …
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