Scalable architecture for high density CPLDS having two-level hierarchy of routing resources
OP Agrawal, CA Stanley, XW He, LR Metzger… - US Patent …, 2001 - Google Patents
An improved, scalable CPLD device has a two-tiered hier archical Switch construct
comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch …
comprised of a Global Switch Matrix (GSM) and an even number of Segment Switch …
Computational field programmable architecture
AS Kaviani, SD Brown - US Patent 6,140,839, 2000 - Google Patents
A computational field programable architecture targeted for compute intensive applications.
The architecture is hierarchical and includes, for implementation of data path circuits …
The architecture is hierarchical and includes, for implementation of data path circuits …
Graphical user interface for dynamically reconfiguring a programmable device
MA Pleis, KY Ogami, M Zhaksilikov - US Patent 8,527,949, 2013 - Google Patents
Appl'NO" 13/182'431 An interface, system and method enabling dynamic recon (22) Filed:
JUL 13, 2011? guration of electronic device in a convenient and ef? cient manner. The …
JUL 13, 2011? guration of electronic device in a convenient and ef? cient manner. The …
Programmable logic device
TM Lacey, DL Johnson - US Patent 6,864,710, 2005 - Google Patents
(57) ABSTRACT A programmable logic device comprising one or more horizontal routing
channels, one or more vertical routing channels, and a logic element. Each logic element …
channels, one or more vertical routing channels, and a logic element. Each logic element …
Input/output multiplexer bus
DR Sequine - US Patent 8,067,948, 2011 - Google Patents
(57) ABSTRACT An input/output (“I/O) system includes a plurality of input/output (“I/O) ports,
measurement circuitry, and an I/O mul tiplexer bus. The measurement circuitry is coupled to …
measurement circuitry, and an I/O mul tiplexer bus. The measurement circuitry is coupled to …
System level interconnect with programmable switching
B Sullam, W Snyder, H Mohammed - US Patent 8,026,739, 2011 - Google Patents
4,608.502 4,647,169 4,656,603 4,670,838 4,689,740 4,692,718 4,701,907 4,727,541
4,736,097 4,740,966 4,755,766 4,773,024 4,794,558 4,802,103 4,802,119 4,807, 183 …
4,736,097 4,740,966 4,755,766 4,773,024 4,794,558 4,802,103 4,802,119 4,807, 183 …
Temperature sensor with digital bandgap
G Venkataraman, H Kutz, M Mar - US Patent 8,092,083, 2012 - Google Patents
(57) ABSTRACT A system comprises a temperature sensor generate multiple base-emitter
Voltage signals by sequentially providing Vari ous currents to a transistor, and a system …
Voltage signals by sequentially providing Vari ous currents to a transistor, and a system …
Power management architecture, method and configuration system
KY Ogami - US Patent 8,078,894, 2011 - Google Patents
3,600,690 A 8/1971 White 3,725,804 A 4/1973 Langan 3,740,588 A 6/1973 Stratton et a1.
3,810,036 A 5/1974 Bloedorn 3,831,113 A 8/1974 Ahmed 3,845,328 A 10/1974 …
3,810,036 A 5/1974 Bloedorn 3,831,113 A 8/1974 Ahmed 3,845,328 A 10/1974 …
Configurable memory for programmable logic circuits
TM Lacey, DL Johnson - US Patent 6,388,464, 2002 - Google Patents
An apparatus comprising a memory device and a programmable logic device. The memory
device may be configured to (i) connect to a first bus and a second bus and (ii) operate in …
device may be configured to (i) connect to a first bus and a second bus and (ii) operate in …
Programmable microcontroller architecture
W Snyder - US Patent 8,176,296, 2012 - Google Patents
US PATENT DOCUMENTS 3,600,690 A 8, 1971 White 3,725,804 A 4, 1973 Langan
3,740,588 A 6, 1973 Stratton et al. 3,805,245 A 4, 1974 Brooks et al. 3,810,036 A 5, 1974 …
3,740,588 A 6, 1973 Stratton et al. 3,805,245 A 4, 1974 Brooks et al. 3,810,036 A 5, 1974 …