Lightweight hamming product code based multiple bit error correction coding scheme using shared resources for on chip interconnects
AK Chlaab, WN Flayyih, FZ Rokhani - Bulletin of Electrical Engineering and …, 2020 - beei.org
In this paper, we present multiple bit error correction coding scheme based on extended
Hamming product code combined with type II HARQ using shared resources for on chip …
Hamming product code combined with type II HARQ using shared resources for on chip …
[PDF][PDF] Reliability analysis of multibit error correcting coding and comparison to hamming product code for on-chip interconnect
AK Chlaab, WN Flayyih, FZ Rokhani - Journal of Engineering, 2020 - iasj.net
Error control schemes became a necessity in network-on-chip (NoC) to improve reliability as
the on-chip interconnect errors increase with the continuous shrinking of geometry …
the on-chip interconnect errors increase with the continuous shrinking of geometry …
Low Power 90 nm 8× 4 Pseudo NMOS Barrel Shifter Design
JSD Vudatha, SP Rajeev… - 2021 5th International …, 2021 - ieeexplore.ieee.org
In this paper, the authors implemented an 8× 4 barrel shifter using two MOS logics: static
CMOS and pseudo NMOS. Cadence Virtuoso is used for simulation at 90nm technology …
CMOS and pseudo NMOS. Cadence Virtuoso is used for simulation at 90nm technology …
VLSI Design of Low Power Barrel Shifter using 90 nm TG technology
JSD Vudatha, N Kota, P Gutha… - … , Signals & Systems …, 2021 - ieeexplore.ieee.org
The barrel shifter is known for the manipulation of various bits in a single clock cycle. In this
paper, an 8*4 barrel shifter is designed using transmission gate technology. The design and …
paper, an 8*4 barrel shifter is designed using transmission gate technology. The design and …