Congestion control and QoS in NoC by regulating the injection traffic
S Kumar, E Norige - US Patent 9,571,402, 2017 - Google Patents
Abstract Systems and methods described herein are directed to solutions for NoC
interconnects that provide congestion avoidance and end-to-end uniform and weighted-fair …
interconnects that provide congestion avoidance and end-to-end uniform and weighted-fair …
Asymmetric mesh NoC topologies
GO6F 3/40(2006.01) f lan for a N k on Chi C 1 h GO6F 5/78 (2006.01) oor plan for a Network
on Chip (NoC) topology that can include a plurality of on chip blocks of substantially non …
on Chip (NoC) topology that can include a plurality of on chip blocks of substantially non …
Asymmetric mesh NoC topologies
Example implementations described herein are directed to a system on chip (SoC) that can
include a plurality of blocks of substantially non-uniform shapes and dimensions, a plurality …
include a plurality of blocks of substantially non-uniform shapes and dimensions, a plurality …
Streaming bridge design with host interfaces and network on chip (NoC) layers
R Chopra, S Kumar - US Patent 9,699,079, 2017 - Google Patents
Abstract Systems and methods described herein are directed to streaming bridge design
implementations that help interconnect and transfer transaction packets between multiple …
implementations that help interconnect and transfer transaction packets between multiple …
Heterogeneous channel capacities in an interconnect
Abstract Systems and methods involving construction of a system interconnect in which
different channels have different widths in numbers of bits. Example processes to construct …
different channels have different widths in numbers of bits. Example processes to construct …
Hardware and software enabled implementation of power profile management instructions in system on chip
R Kaushal, A Gangwar, VM Pusuluri… - US Patent 9,568,970, 2017 - Google Patents
Aspects of the present disclosure relate to a method and system for hybrid and/or distributed
implementation of generation and/or execution of power profile management instructions …
implementation of generation and/or execution of power profile management instructions …
Combining associativity and cuckoo hashing
J Philip, S Kumar, J Rowlands - US Patent 9,223,711, 2015 - Google Patents
Addition, search, and performance of other allied activities relating to keys are performed in
a hardware hash table. Further, high performance and efficient design may be pro vided for …
a hardware hash table. Further, high performance and efficient design may be pro vided for …
Configurable router for a network on chip (NoC)
J Philip, S Kumar - US Patent 9,742,630, 2017 - Google Patents
Example implementations described herein are directed to a configurable building block,
such as a router, for implementation of a Network on Chip (NoC). The router is …
such as a router, for implementation of a Network on Chip (NoC). The router is …
Reconfigurable NoC for customizing traffic and optimizing performance after NoC synthesis
S Kumar, E Norige - US Patent 8,934,377, 2015 - Google Patents
8,136,071 8,281.297 8,312.402 8.448, 102 8.492. 886 8,541,819 8,543,964 8,601.423
8,635,577 8,667,439 8,717,875 2002fOO71392 2002fOO73380 2002fO095430 …
8,635,577 8,667,439 8,717,875 2002fOO71392 2002fOO73380 2002fO095430 …
Automatic pipelining of NoC channels to meet timing and/or performance
S Kumar - US Patent 9,158,882, 2015 - Google Patents
US9158882B2 - Automatic pipelining of NoC channels to meet timing and/or performance -
Google Patents US9158882B2 - Automatic pipelining of NoC channels to meet timing and/or …
Google Patents US9158882B2 - Automatic pipelining of NoC channels to meet timing and/or …