Reception of 4-level pulse amplitude modulation (PAM-4) requires a clock and data
recovery (CDR) circuit, typically implemented by a PLL-like structure. An essential block in …

The upcoming 100 Gb/s links in the next-generation ethernet passive optical networks will
be based on four channels of 25 Gb/s. The corresponding transceivers in these optical links …

The choice of clock and data recovery (CDR) architecture in serial links dictates many of the
blocklevel circuit specifications (specs). Block-level specs ultimately determine the energy …

Recently, there has been a strong drive to replace established analog circuits for multi-
gigabit clock and data recovery (CDR) by more digital solutions. We focused on phase …

To address the problem of gear clearance causing the limit cycle oscillation at the
positioning end, further deteriorating the positioning accuracy of the servo system, and even …

We report on the development of a time-domain numerical modeling framework to estimate
timing jitter in High-Speed Serial Interfaces (HSSI) including a wide range of effects such as …

In this paper we consider almost cyclostationary processes with jitter effect. We propose a
bootstrap approach based on the Moving Block Bootstrap method to construct pointwise and …

This paper devotes to the robust stability problem for an uncertain linear time invariant (LTI)
feedback system with actuator saturation nonlinearity. Based on a three degree of freedom …

In this paper, we introduce a statistical approach for studying a special class of nonlinear
dynamical systems such as ADPLLs and ADPLL networks, where the process driving the …

This paper presents a high speed dual channel 12.5 Gbps receiver for serial link
communication. Each channel consists of a continuous time linear equalizer (CTLE), a novel …