Graphpim: Enabling instruction-level pim offloading in graph computing frameworks
With the emergence of data science, graph computing has become increasingly important
these days. Unfortunately, graph computing typically suffers from poor performance when …
these days. Unfortunately, graph computing typically suffers from poor performance when …
DRAMsim3: A cycle-accurate, thermal-capable DRAM simulator
DRAM technology has developed rapidly in recent years. Several industrial solutions offer
3D packaging of DRAM and some are envisioning the integration of CPU and DRAM on the …
3D packaging of DRAM and some are envisioning the integration of CPU and DRAM on the …
The gem5 simulator: Version 20.0+
The open-source and community-supported gem5 simulator is one of the most popular tools
for computer architecture research. This simulation infrastructure allows researchers to …
for computer architecture research. This simulation infrastructure allows researchers to …
DRAMSim2: A cycle accurate memory system simulator
P Rosenfeld, E Cooper-Balis… - IEEE computer …, 2011 - ieeexplore.ieee.org
In this paper we present DRAMSim2, a cycle accurate memory system simulator. The goal of
DRAMSim2 is to be an accurate and publicly available DDR2/3 memory system model …
DRAMSim2 is to be an accurate and publicly available DDR2/3 memory system model …
On the role of burst buffers in leadership-class storage systems
The largest-scale high-performance (HPC) systems are stretching parallel file systems to
their limits in terms of aggregate bandwidth and numbers of clients. To further sustain the …
their limits in terms of aggregate bandwidth and numbers of clients. To further sustain the …
5 petabyte simulation of a 45-qubit quantum circuit
T Häner, DS Steiger - Proceedings of the International Conference for …, 2017 - dl.acm.org
Near-term quantum computers will soon reach sizes that are challenging to directly simulate,
even when employing the most powerful supercomputers. Yet, the ability to simulate these …
even when employing the most powerful supercomputers. Yet, the ability to simulate these …
The McPAT framework for multicore and manycore architectures: Simultaneously modeling power, area, and timing
This article introduces McPAT, an integrated power, area, and timing modeling framework
that supports comprehensive design space exploration for multicore and manycore …
that supports comprehensive design space exploration for multicore and manycore …
qHiPSTER: The quantum high performance software testing environment
M Smelyanskiy, NPD Sawaya… - arXiv preprint arXiv …, 2016 - arxiv.org
We present qHiPSTER, the Quantum High Performance Software Testing Environment.
qHiPSTER is a distributed high-performance implementation of a quantum simulator on a …
qHiPSTER is a distributed high-performance implementation of a quantum simulator on a …
Graphpulse: An event-driven hardware accelerator for asynchronous graph processing
S Rahman, N Abu-Ghazaleh… - 2020 53rd Annual IEEE …, 2020 - ieeexplore.ieee.org
Graph processing workloads are memory intensive with irregular access patterns and large
memory footprint resulting in low data locality. Their popular software implementations …
memory footprint resulting in low data locality. Their popular software implementations …
Survey of CPU and memory simulators in computer architecture: A comprehensive analysis including compiler integration and emerging technology applications
In computer architecture studies, simulators are crucial for design verification, reducing
research and development time and ensuring the high accuracy of verification results …
research and development time and ensuring the high accuracy of verification results …