Pushing the level of abstraction of digital system design: A survey on how to program fpgas
Field Programmable Gate Arrays (FPGAs) are spatial architectures with a heterogeneous
reconfigurable fabric. They are state-of-the-art for prototyping, telecommunications …
reconfigurable fabric. They are state-of-the-art for prototyping, telecommunications …
Dsagen: Synthesizing programmable spatial accelerators
Domain-specific hardware accelerators can provide orders of magnitude speedup and
energy efficiency over general purpose processors. However, they require extensive manual …
energy efficiency over general purpose processors. However, they require extensive manual …
Hardware acceleration of sparse and irregular tensor computations of ml models: A survey and insights
Machine learning (ML) models are widely used in many important domains. For efficiently
processing these computational-and memory-intensive applications, tensors of these …
processing these computational-and memory-intensive applications, tensors of these …
A compiler infrastructure for accelerator generators
We present Calyx, a new intermediate language (IL) for compiling high-level programs into
hardware designs. Calyx combines a hardware-like structural language with a software-like …
hardware designs. Calyx combines a hardware-like structural language with a software-like …
OverGen: Improving FPGA usability through domain-specific overlay generation
FPGAs have been proven to be powerful computational accelerators across many types of
workloads. The mainstream programming approach is high level synthesis (HLS), which …
workloads. The mainstream programming approach is high level synthesis (HLS), which …
LLHD: A multi-level intermediate representation for hardware description languages
Modern Hardware Description Languages (HDLs) such as SystemVerilog or VHDL are, due
to their sheer complexity, insufficient to transport designs through modern circuit design …
to their sheer complexity, insufficient to transport designs through modern circuit design …
Archytas: A framework for synthesizing and dynamically optimizing accelerators for robotic localization
Despite many recent efforts, accelerating robotic computing is still fundamentally
challenging for two reasons. First, robotics software stack is extremely complicated …
challenging for two reasons. First, robotics software stack is extremely complicated …
Taskstream: Accelerating task-parallel workloads by recovering program structure
V Dadu, T Nowatzki - Proceedings of the 27th ACM International …, 2022 - dl.acm.org
Reconfigurable accelerators, like CGRAs and dataflow architectures, have come to
prominence for addressing data-processing problems. However, they are largely limited to …
prominence for addressing data-processing problems. However, they are largely limited to …
HECTOR: A multi-level intermediate representation for hardware synthesis methodologies
Hardware synthesis requires a complicated process to generate synthesizable register
transfer level (RTL) code. High-level synthesis tools can automatically transform a high-level …
transfer level (RTL) code. High-level synthesis tools can automatically transform a high-level …
Challenges and opportunities of security-aware EDA
J Feldtkeller, P Sasdrich, T Güneysu - ACM Transactions on Embedded …, 2023 - dl.acm.org
The foundation of every digital system is based on hardware in which security, as a core
service of many applications, should be deeply embedded. Unfortunately, the knowledge of …
service of many applications, should be deeply embedded. Unfortunately, the knowledge of …