Within the last decade, considerable efforts have been devoted to fabricating transistors
utilizing 2D semiconductors. Also, small circuits consisting of a few transistors have been …

We review the state-of-the-art in the understanding of planar NAND Flash memory reliability
and discuss how the recent move to three-dimensional (3D) devices has affected this field …

In this letter, we present clear experimental evidence proving that a high-temperature
idle/data-retention phase gives rise to a permanent intensification of random telegraph noise …

This paper investigates the temperature dependence of random telegraph noise (RTN) in 3-
D NAND Flash technologies. Experimental results on memory arrays reveal an increase of …

In this paper, we review the phenomenology of random telegraph noise (RTN) in 3D NAND
Flash arrays. The main features of such arrays resulting from their mainstream integration …

In this paper, we compare results from atomistic and continuous simulation of
decananometer scale CMOS transistors. We study the behavior of important figures of merit …

In this paper, we compare quantitatively the results obtained from the numerical simulation
of current transport in polysilicon-channel MOSFETs under different modeling assumptions …

In this paper we present a reliability simulation framework from atomistic simulations up to
circuit simulations, including traps interactions with variability sources. Trapping and …

We report a thorough 3-D simulation study of the correlation between multiple, trapped
charges in the gate oxide of nanoscale bulk MOSFETs under bias and temperature …

Relentless performance and density scaling of modern CMOS devices has come at the
expense of circuit stability and variability. In this paper, we specifically reveal how switching …