Performance, metastability, and soft-error robustness trade-offs for flip-flops in 40 nm CMOS

D Rennie, D Li, M Sachdev, BL Bhuva… - … on Circuits and …, 2012 - ieeexplore.ieee.org
In modern CMOS processes, soft errors and metastability are two prominent failure
mechanisms. Radiation induced single event upsets, or soft-errors, have become a …

A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage …

C Lin, W He, Y Sun, L Shao, B Zhang… - IEEE Journal of Solid …, 2023 - ieeexplore.ieee.org
For a network-on-chip (NoC) with multiple voltage/frequency domains, metastability hurts the
reliability during the clock-domain crossing, especially in the near-threshold-voltage (NTV) …

MEDAC: A metastability condition detection and correction technique for a near-threshold-voltage multi-voltage-/frequency-domain network-on-chip

C Lin, W He, Y Sun, B Pei, PK Chundi… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
This article presents a technique titled metastability condition detection and correction
(MEDAC) that is featured in a near-threshold voltage (NTV) network-on-chip (NoC) …

Soft-error-tolerant design methodology for balancing performance, power, and reliability

HM Chou, MY Hsiao, YC Chen… - … Transactions on Very …, 2014 - ieeexplore.ieee.org
Soft error has become an important reliability issue in advanced technologies. To tolerate
soft errors, solutions suggested in previous works incur significant performance and power …

Designing tunable subthreshold logic circuits using adaptive feedback equalization

M Zangeneh, A Joshi - IEEE Transactions on Very Large Scale …, 2015 - ieeexplore.ieee.org
Ultralow-power subthreshold logic circuits are becoming prominent in embedded
applications with limited energy budgets. Minimum energy consumption of digital logic …

Hardening C-elements against metastability

LS Heck, MT Moreira… - 2017 24th IEEE …, 2017 - ieeexplore.ieee.org
C-elements are non-standard sequential logic gates employed in the design of eg
asynchronous circuits, clock generators and radiation-hardened circuits. Like any other …

Analysis of the impact of metastability phenomenon on the latency and power consumption of synchronizer circuits

V Melikyan, E Babayan, T Khazhakyan… - 2016 IEEE East …, 2016 - ieeexplore.ieee.org
In modern System on Chips (SoCs) different blocks may use clock signals with different
frequencies, in which case SoC is said to have multiple clock domains. The signal that …

Dynamic synchronizer flip-flop performance in FinFET technologies

M Buckler, A Vaidya, X Liu… - 2014 Eighth IEEE/ACM …, 2014 - ieeexplore.ieee.org
The use of fine-grain Dynamic Voltage and Frequency Scaling (DVFS) has increased the
number of distinct clock domains on a given Network-on-Chip (NoC). This necessitates …

Synchronizer with controlled metastability characteristics

MY Semenov, VM Mikhailov, SV Somov… - US Patent …, 2020 - Google Patents
Synchronizer circuits having controllable metastability are provided, one of which includes: a
first flip-flop circuit comprising a first master latch connected in series with a first slave latch; …

Designing energy-efficient sub-threshold logic circuits using equalization and non-volatile memory circuits using memristors

M Zangeneh - 2015 - search.proquest.com
The very large scale integration (VLSI) community has utilized aggressive complementary
metal-oxide semiconductor (CMOS) technology scaling to meet the ever-increasing …