RevSCA: Using reverse engineering to bring light into backward rewriting for big and dirty multipliers
In recent years, formal methods based on Symbolic Computer Algebra (SCA) have shown
very good results in verification of integer multipliers. The success is based on removing …
very good results in verification of integer multipliers. The success is based on removing …
Efficient modular hybrid adders and Radix-4 booth multipliers for DSP applications
P Patali, ST Kassim - Microelectronics Journal, 2020 - Elsevier
Adders and multipliers are the fundamental elements of a signal processing architecture.
Improve the speed of addition and multiplication operations while minimizing power …
Improve the speed of addition and multiplication operations while minimizing power …
High throughput FIR filter architectures using retiming and modified CSLA based adders
P Patali… - IET Circuits, Devices & …, 2019 - Wiley Online Library
A methodology to improve the throughput of FIR filters through the effective use of retiming
and efficient add–multiply operation is presented in this study. Delay, energy and area …
and efficient add–multiply operation is presented in this study. Delay, energy and area …
High speed and ultra low power design of carry-out bit of 4-bit carry look-ahead adder
A new carry generation scheme for carry out bit of a 4-bit carry look-ahead (CLA) adder is
presented. To analyze performance, proposed design for carry-out bit was implemented and …
presented. To analyze performance, proposed design for carry-out bit was implemented and …
Delay and energy efficient modular hybrid adder for signal processor architectures
P Pramod, TK Shahana - IETE Journal of Research, 2022 - Taylor & Francis
In this modern era, high-performance energy efficient devices/systems are the basic
requirement for most of the real-time applications. Multiply-accumulate (MAC) units are the …
requirement for most of the real-time applications. Multiply-accumulate (MAC) units are the …
Design and implementation of 16 tap FIR filter for DSP applications
NS Rai, P Shree, YP Meghana… - … on Advances in …, 2018 - ieeexplore.ieee.org
In this paper, two novel methods to design a high speed, low power 16-Tap 32-bit digital FIR
filter for DSP application are proposed. The basic building blocks of the FIR filters are …
filter for DSP application are proposed. The basic building blocks of the FIR filters are …
Degradation mitigation effects of pressure swing in proton exchange membrane fuel cells with dead-ended anode
High cost remains to be one of the primary obstacles for the commercialization of proton
exchange membrane fuel cells (PEMFCs). To simplify the fuel cell system and reduce cost …
exchange membrane fuel cells (PEMFCs). To simplify the fuel cell system and reduce cost …
Hardware efficient approximate multiplier architecture for image processing applications
S Chandaka, B Narayanam - Journal of Electronic Testing, 2022 - Springer
In this research paper, approximate multipliers are designed to reduce the computational
time and power delay product. However, there is a high possibility to further optimize the …
time and power delay product. However, there is a high possibility to further optimize the …
Power and delay efficient fir filter design using ESSA and VL-CSKA based booth multiplier
FIR filter plays a major role in digital image processing applications. The power and delay
performance of any FIR filter depends on the switching activities between the filter …
performance of any FIR filter depends on the switching activities between the filter …
High-speed and energy efficient carry select adder (CSLA) dominated by carry generation logic
M Nam, Y Choi, K Cho - Microelectronics Journal, 2018 - Elsevier
This paper presents a high-speed, energy efficient carry select adder (CSLA) dominated by
carry generation logics. The proposed architecture is composed of three functional stages–a …
carry generation logics. The proposed architecture is composed of three functional stages–a …