Dreamplace: Deep learning toolkit-enabled gpu acceleration for modern vlsi placement
Placement for very-large-scale integrated (VLSI) circuits is one of the most important steps
for design closure. This paper proposes a novel GPU-accelerated placement framework …
for design closure. This paper proposes a novel GPU-accelerated placement framework …
Progress of Placement Optimization for Accelerating VLSI Physical Design
Placement is essential in very large-scale integration (VLSI) physical design, as it directly
affects the design cycle. Despite extensive prior research on placement, achieving fast and …
affects the design cycle. Despite extensive prior research on placement, achieving fast and …
Abcdplace: Accelerated batch-based concurrent detailed placement on multithreaded cpus and gpus
Placement is an important step in modern verylarge-scale integrated (VLSI) designs.
Detailed placement is a placement refining procedure intensively called throughout the …
Detailed placement is a placement refining procedure intensively called throughout the …
DREAMPlace 3.0: Multi-electrostatics based robust VLSI placement with region constraints
Placement is a critical step for modern very-large-scale integrated (VLSI) design closure.
Recently, electrostatics-based analytical placement frameworks (ePlace) demonstrate …
Recently, electrostatics-based analytical placement frameworks (ePlace) demonstrate …
Differentiable-timing-driven global placement
Placement is critical to the timing closure of the very-large-scale integrated (VLSI) circuit
design flow. This paper proposes a differentiable-timing-driven global placement framework …
design flow. This paper proposes a differentiable-timing-driven global placement framework …
Integrating operations research into very large-scale integrated circuits placement design: A review
The placement stage of the physical design of very large-scale integrated circuits (VLSI)
specifies the arrangement and order of standard cells and devices within an area, and the …
specifies the arrangement and order of standard cells and devices within an area, and the …
High-performance placement for large-scale heterogeneous FPGAs with clock constraints
Z Zhu, Y Mei, Z Li, J Lin, J Chen, J Yang… - Proceedings of the 59th …, 2022 - dl.acm.org
With the increasing complexity of the field-programmable gate array (FPGA) architecture,
heterogeneity and clock constraints have greatly challenged FPGA placement. In this paper …
heterogeneity and clock constraints have greatly challenged FPGA placement. In this paper …
High-performance Placement Engine for Modern Large-scale FPGAs With Heterogeneity and Clock Constraints
As field-programmable gate array (FPGA) architectures continue to evolve and become
more complex, the heterogeneity and clock constraints imposed by modern FPGAs have …
more complex, the heterogeneity and clock constraints imposed by modern FPGAs have …
iPL-3D: A Novel Bilevel Programming Model for Die-to-Die Placement
X Zhao, S Chen, Y Qiu, J Li, Z Huang… - 2023 IEEE/ACM …, 2023 - ieeexplore.ieee.org
Die-to-die (D2D) placement is a more challenging stage in achieving higher performance
with complex constraints, critically impacting timing, power, yield, cost, etc. Existing placers …
with complex constraints, critically impacting timing, power, yield, cost, etc. Existing placers …
An iterated local search algorithm for solving large-scale instances of the duplex arrangement problem
ARS Amaral - Engineering Optimization, 2024 - Taylor & Francis
The minimum multiplex arrangement problem locates each vertex of a graph on an integer
point on a line, with each integer point being assigned at most m vertices. The case with m …
point on a line, with each integer point being assigned at most m vertices. The case with m …