Methods for fault tolerance in networks-on-chip
Networks-on-Chip constitute the interconnection architecture of future, massively parallel
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …
multiprocessors that assemble hundreds to thousands of processing cores on a single chip …
[图书][B] Semiconductor material and device characterization
DK Schroder - 2015 - books.google.com
This Third Edition updates a landmark text with the latest findings The Third Edition of the
internationally lauded Semiconductor Material and Device Characterization brings the text …
internationally lauded Semiconductor Material and Device Characterization brings the text …
Facelift: Hiding and slowing down aging in multicores
A Tiwari, J Torrellas - 2008 41st IEEE/ACM International …, 2008 - ieeexplore.ieee.org
Processors progressively age during their service life due to normal workload activity. Such
aging results in gradually slower circuits. Anticipating this fact, designers add timing …
aging results in gradually slower circuits. Anticipating this fact, designers add timing …
[图书][B] The VLSI handbook
WK Chen - 1999 - taylorfrancis.com
Over the years, the fundamentals of VLSI technology have evolved to include a wide range
of topics and a broad range of practices. To encompass such a vast amount of knowledge …
of topics and a broad range of practices. To encompass such a vast amount of knowledge …
Reliability-and process-variation aware design of integrated circuits
M Alam - Microelectronics Reliability, 2008 - Elsevier
We review the literature for reliability-and process-variation aware VLSI design to find that
an exciting area of research/application is rapidly emerging as a core topic of IC design …
an exciting area of research/application is rapidly emerging as a core topic of IC design …
Paceline: Improving single-thread performance in nanoscale cmps through core overclocking
B Greskamp, J Torrellas - 16th International Conference on …, 2007 - ieeexplore.ieee.org
Under current worst-case design practices, manufacturers specify conservative values for
processor frequencies in order to guarantee correctness. To recover some of the lost …
processor frequencies in order to guarantee correctness. To recover some of the lost …
Multiphoton photoemission and electric-field-induced optical second-harmonic generation as probes of charge transfer across the interface
JG Mihaychuk, N Shamir, HM Van Driel - Physical Review B, 1999 - APS
Multiphoton photoemission (MPPE) and electric field-induced second-harmonic generation
(EFISH) are used as complementary in situ probes of light-induced electron transfer across …
(EFISH) are used as complementary in situ probes of light-induced electron transfer across …
On the mechanism for interface trap generation in MOS transistors due to channel hot carrier stressing
The classical concept and theory suggest that the degradation of MOS transistors is caused
by interface trap generation resulting from" hot carrier injection." We report three new …
by interface trap generation resulting from" hot carrier injection." We report three new …
Comprehensive analysis of sub-20 nm black phosphorus based junctionless-recessed channel MOSFET for analog/RF applications
In this work, a comprehensive analog and RF performance of a novel Black Phosphorus-
Junctionless-Recessed Channel (BP-JL-RC) MOSFET has been explored at 45 nm …
Junctionless-Recessed Channel (BP-JL-RC) MOSFET has been explored at 45 nm …
[PDF][PDF] Scaled CMOS technology reliability users guide
M White - 2010 - Citeseer
The desire to assess the reliability of emerging scaled microelectronics technologies
through faster reliability trials and more accurate acceleration models is the precursor for …
through faster reliability trials and more accurate acceleration models is the precursor for …