T-CREST: Time-predictable multi-core architecture for embedded systems

M Schoeberl, S Abbaspour, B Akesson… - Journal of Systems …, 2015 - Elsevier
Real-time systems need time-predictable platforms to allow static analysis of the worst-case
execution time (WCET). Standard multi-core processors are optimized for the average case …

A software memory partition approach for eliminating bank-level interference in multicore systems

L Liu, Z Cui, M Xing, Y Bao, M Chen, C Wu - Proceedings of the 21st …, 2012 - dl.acm.org
Main memory system is a shared resource in modern multicore machines, resulting in
serious interference, which causes performance degradation in terms of throughput …

A comprehensive approach to DRAM power management

I Hur, C Lin - 2008 IEEE 14th International Symposium on High …, 2008 - ieeexplore.ieee.org
This paper describes a comprehensive approach for using the memory controller to improve
DRAM energy efficiency and manage DRAM power. We make three contributions:(1) we …

Intelligent architectures for intelligent computing systems

O Mutlu - 2021 Design, Automation & Test in Europe …, 2021 - ieeexplore.ieee.org
Computing is bottlenecked by data. Large amounts of application data overwhelm storage
capability, communication capability, and computation capability of the modern machines …

Dynamic command scheduling for real-time memory controllers

Y Li, B Akesson, K Goossens - 2014 26th Euromicro …, 2014 - ieeexplore.ieee.org
Memory controller design is challenging as real-time embedded systems feature an
increasing diversity of real-time and non-real-time applications with variable transaction …

Memory-efficient on-chip network with adaptive interfaces

M Daneshtalab, M Ebrahimi, P Liljeberg… - … on Computer-Aided …, 2011 - ieeexplore.ieee.org
To achieve higher memory bandwidth in network-based multiprocessor architectures,
multiple dynamic random access memories can be accessed simultaneously. In such …

Intelligent architectures for intelligent machines

O Mutlu - 2020 International Symposium on VLSI Design …, 2020 - ieeexplore.ieee.org
Computing is bottlenecked by data. Large amounts of application data overwhelm storage
capability, communication capability, and computation capability of the modern machines …

An SDRAM-aware router for networks-on-chip

W Jang, DZ Pan - Proceedings of the 46th Annual Design Automation …, 2009 - dl.acm.org
In this paper, we present an NoC (Networks-on-Chip) router with an SDRAM-aware flow
control. Based on a priority-based arbitration, it schedules packets to improve memory …

BPM/BPM+ Software-based dynamic memory partitioning mechanisms for mitigating DRAM bank-/channel-level interferences in multicore systems

L Liu, Z Cui, Y Li, Y Bao, M Chen, C Wu - ACM Transactions on …, 2014 - dl.acm.org
The main memory system is a shared resource in modern multicore machines that can result
in serious interference leading to reduced throughput and unfairness. Many new memory …

Architecture and analysis of a dynamically-scheduled real-time memory controller

Y Li, B Akesson, K Goossens - Real-Time Systems, 2016 - Springer
Memory controller design is challenging as mixed time-criticality embedded systems feature
an increasing diversity of real-time (RT) and non-real-time (NRT) applications with variable …