Aliased mode for cache controller
AA Chachad, TD Anderson, PK Swami… - US Patent …, 2022 - Google Patents
An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to
the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the …
the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the …
Pipeline arbitration
AA Chachad, DM Thompson - US Patent 12,014,206, 2024 - Google Patents
A method includes receiving, by a first stage in a pipeline, a first transaction from a previous
stage in pipeline; in response to first transaction comprising a high priority transaction …
stage in pipeline; in response to first transaction comprising a high priority transaction …
Aliased mode for cache controller
AA Chachad, TD Anderson, PK Swami… - US Patent …, 2024 - Google Patents
An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to
the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the …
the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the …
Pipeline arbitration
AA Chachad, DM Thompson - US Patent 11,461,127, 2022 - Google Patents
A method includes receiving, by a first stage in a pipeline, a first transaction from a previous
stage in pipeline; in response to first transaction comprising a high priority transaction …
stage in pipeline; in response to first transaction comprising a high priority transaction …