[图书][B] VLSI test principles and architectures: design for testability
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …
design a testable and quality product, drive down test cost, improve product quality and …
[图书][B] The Electrical Engineering Handbook-Six Volume Set
RC Dorf - 2018 - api.taylorfrancis.com
In two editions spanning more than a decade, The Electrical Engineering Handbook stands
as the definitive reference to the multidisciplinary field of electrical engineering. Our …
as the definitive reference to the multidisciplinary field of electrical engineering. Our …
[PDF][PDF] Model for Delay Faults Based Upon Paths.
GL Smith - ITC, 1985 - Citeseer
Delay testing of combinational logic in a clocked environment is analyzed. A model based
upon paths is introduced for delay faults. Any path with a total delay exceeding the clock …
upon paths is introduced for delay faults. Any path with a total delay exceeding the clock …
[图书][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
On delay fault testing in logic circuits
CJ Lin, SM Reddy - … Transactions on Computer-Aided Design of …, 1987 - ieeexplore.ieee.org
Correct operation of a logic circuit requires propagation delays of all paths in the circuit to be
smaller than the intended" clock interval." Random or deterministic tests, conducted at the …
smaller than the intended" clock interval." Random or deterministic tests, conducted at the …
Design for testability: Using scanpath techniques for path-delay test and measurement
BI Dervisoglu, GE Stong - Proceedings of the IEEE International Test …, 1991 - dl.acm.org
Design for Testability | Proceedings of the IEEE International Test Conference on Test: Faster,
Better, Sooner skip to main content ACM Digital Library home ACM Association for Computing …
Better, Sooner skip to main content ACM Digital Library home ACM Association for Computing …
On path selection in combinational logic circuits
In order to ascertain correct operation of digital logic circuits it is necessary to verify correct
functional operation as well as correct operation at desired clock rates. To ascertain correct …
functional operation as well as correct operation at desired clock rates. To ascertain correct …
Classification and identification of nonrobust untestable path delay faults
KT Cheng, HC Chen - … on Computer-Aided Design of Integrated …, 1996 - ieeexplore.ieee.org
Recently published results have shown that, for many circuits, only a small percentage of
path delay faults is robust testable, Among the robust untestable faults, a significant …
path delay faults is robust testable, Among the robust untestable faults, a significant …
On the detection of delay faults
AK Pramanick, SM Reddy - International Test Conference 1988 …, 1988 - ieeexplore.ieee.org
The class of faults known as gate delay faults are investigated. A taxonomy of the classes of
gate delay fault detecting tests is provided. Methods to derive robust and nonrobust tests to …
gate delay fault detecting tests is provided. Methods to derive robust and nonrobust tests to …
Transition fault testing for sequential circuits
KT Cheng - IEEE Transactions on Computer-Aided Design of …, 1993 - ieeexplore.ieee.org
Addresses the problem of simulating and generating tests for transition faults in nonscan
and partial scan synchronous sequential circuits. A transition fault model for sequential …
and partial scan synchronous sequential circuits. A transition fault model for sequential …