Apparatus and methods for clock synchronization and fre quency translation are provided
herein. Clock synchroniza tion and frequency translation integrated circuits (ICs) gen erate …

Apparatus and methods for clock synchronization and frequency translation are provided
herein. Clock synchronization and frequency translation integrated circuits (ICs) generate …

A phase locked loop (PLL) device is configurable in an analog phase locked loop and a
hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an …

BACKGROUND Electronic devices (cellular telephones, wireless modems, computers,
digital music players, Global Positioning System units, Personal Digital Assistants, gaming …

A system and method for clock phase alignment at a plurality of line cards over a backplane
of a communication system. Phase adjustments are continually made for the clock signals at …

(57) ABSTRACT A method for controlling a digital fractional frequency division phase-locked
loop and a phase-locked loop are disclosed. The phase-locked loop includes a control appa …

BACKGROUND Phase locked loop (PLL) circuits are widely known and used in computers,
radios, telecommunications and many other electronic applications. One of the common …

The present invention is generally directed to a digital clock system that may be used to
generate a clock for a circuit system. In particular, the present invention is directed to a clock …

A phase locked loop (PLL) device is configurable in an analog phase locked loop and a
hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an …

A phase difference between a reference clock signal and a feedback signal is digitally
detected. A resultant phase detection signal is digitally filtered, and a PLL (Phase Locked …