[引用][C] Logic Minimization Algorithms for VLSI Synthesis
RK Brayton - 1984 - books.google.com
The roots of the project which culminates with the writing of this book can be traced to the
work on logic synthesis started in 1979 at the IBM Watson Research Center and at …
work on logic synthesis started in 1979 at the IBM Watson Research Center and at …
[图书][B] Switching theory for logic synthesis
T Sasao - 2012 - books.google.com
Switching Theory for Logic Synthesis covers the basic topics of switching theory and logic
synthesis in fourteen chapters. Chapters 1 through 5 provide the mathematical foundation …
synthesis in fourteen chapters. Chapters 1 through 5 provide the mathematical foundation …
On the complexity of mod-2l sum PLA's
T Sasao, P Besslich - IEEE Transactions on Computers, 1990 - ieeexplore.ieee.org
Consideration is given to the realization of logic functions by using PLAs with an exclusive-
OR (EXOR) array, where a function is represented by mod-2 (EXOR) sum-of-products …
OR (EXOR) array, where a function is represented by mod-2 (EXOR) sum-of-products …
EXMIN2: a simplification algorithm for exclusive-OR-sum-of-products expressions for multiple-valued-input two-valued-output functions
T Sasao - IEEE Transactions on Computer-Aided Design of …, 1993 - ieeexplore.ieee.org
Minimization of AND-EXOR programmable logic arrays (PLAs) with input decoders
corresponds to minimization of the number of products in Exclusive-OR sum-of-products …
corresponds to minimization of the number of products in Exclusive-OR sum-of-products …
A knowledge-based system for designing testable VLSI chips
MS Abadir, MA Breuer - IEEE Design & Test of computers, 1985 - ieeexplore.ieee.org
The complexity of VLSI circuits has increased the need for design for testability (DFT).
Numerous techniques for designing more easily tested circuits have evolved over the years …
Numerous techniques for designing more easily tested circuits have evolved over the years …
The complexity of fault detection problems for combinational logic circuits
Fujiwara, Toida - IEEE Transactions on computers, 1982 - ieeexplore.ieee.org
In this correspondence we analyze the computational complexity of fault detection problems
for combinational circuits and propose an approach to design for testability. Although major …
for combinational circuits and propose an approach to design for testability. Although major …
Implementing a built-in self-test PLA design
R Treuer, H Fujiwara… - IEEE Design & Test of …, 1985 - ieeexplore.ieee.org
An NMOS implementation of a new built-in self-test PLA design is presented. The layouts for
its additional test circuitry result in appoximately 15-percent overhead for most large PlAS, a …
its additional test circuitry result in appoximately 15-percent overhead for most large PlAS, a …
[图书][B] VLSI custom microelectronics: digital: analog, and mixed-signal
SL Hurst - 1998 - taylorfrancis.com
Focuses on the design and production of integrated circuits specifically designed for a
particular application from original equipment manufacturers. The book outlines silicon and …
particular application from original equipment manufacturers. The book outlines silicon and …
A new PLA design for universal testability
H Fujiwara - IEEE transactions on computers, 1984 - ieeexplore.ieee.org
A new design of universally testable PLA's is presented in which all multiple faults can be
detected by a universal test set which is independent of the function being realized by the …
detected by a universal test set which is independent of the function being realized by the …
Lower overhead design for testability of programmable logic arrays
S Bozorgui-Nesbat, EJ McCluskey - IEEE transactions on computers, 1986 - computer.org
A new technique for designing easily testable PLA's is presented. The salient features of this
technique are: 1) low overhead, 2) high fault coverage, 3) simple design, and 4) little or no …
technique are: 1) low overhead, 2) high fault coverage, 3) simple design, and 4) little or no …