Architectures for online error detection and recovery in multicore processors

D Gizopoulos, M Psarakis, SV Adve… - … , Automation & Test …, 2011 - ieeexplore.ieee.org
The huge investment in the design and production of multicore processors may be put at risk
because the emerging highly miniaturized but unreliable fabrication technologies will …

Effective post-silicon validation of system-on-chips using quick error detection

D Lin, T Hong, Y Li, S Eswaran, S Kumar… - … on Computer-Aided …, 2014 - ieeexplore.ieee.org
This paper presents the Quick Error Detection (QED) technique for systematically creating
families of post-silicon validation tests that quickly detect bugs inside processor cores and …

Efficient trace signal selection for post silicon validation and debug

K Basu, P Mishra - 2011 24th Internatioal Conference on VLSI …, 2011 - ieeexplore.ieee.org
Post-silicon validation is an essential part of modern integrated circuit design to capture
bugs and design errors that escape pre-silicon validation phase. A major problem governing …

A survey on post-silicon functional validation for multicore architectures

P Jayaraman, R Parthasarathi - ACM Computing Surveys (CSUR), 2017 - dl.acm.org
During a processor development cycle, post-silicon validation is performed on the first
fabricated chip to detect and fix design errors. Design errors occur due to functional issues …

McVerSi: A test generation framework for fast memory consistency verification in simulation

M Elver, V Nagarajan - 2016 IEEE International Symposium on …, 2016 - ieeexplore.ieee.org
The memory consistency model (MCM), which formally specifies the behaviour of the
memory system, is used by programmers to reason about parallel programs. It is imperative …

Quick detection of difficult bugs for effective post-silicon validation

D Lin, T Hong, F Fallah, N Hakim, S Mitra - Proceedings of the 49th …, 2012 - dl.acm.org
We present a new technique for systematically creating postsilicon validation tests that
quickly detect bugs in processor cores and uncore components (cache controllers, memory …

Mt-sbst: Self-test optimization in multithreaded multicore architectures

N Foutris, M Psarakis, D Gizopoulos… - 2010 IEEE …, 2010 - ieeexplore.ieee.org
Instruction-based or software-based self-testing (SBST) is a scalable functional testing
paradigm that has gained increasing acceptance in testing of single-threaded …

Efficient combination of trace and scan signals for post silicon validation and debug

K Basu, P Mishra, P Patra - 2011 IEEE International Test …, 2011 - ieeexplore.ieee.org
Post-silicon validation is as an important aspect of any integrated circuit design
methodology. The primary objective is to capture the bugs that have escaped the pre-silicon …

Post-silicon bug diagnosis with inconsistent executions

A DeOrio, DS Khudia, V Bertacco - 2011 IEEE/ACM …, 2011 - ieeexplore.ieee.org
The complexity of modern chips intensifies verification challenges, and an increasing share
of this verification effort is shouldered by post-silicon validation. Focusing on the first silicon …

Vulcan: Hardware support for detecting sequential consistency violations dynamically

A Muzahid, S Qi, J Torrellas - 2012 45th Annual IEEE/ACM …, 2012 - ieeexplore.ieee.org
Past work has focused on detecting data races as proxies for Sequential Consistency (SC)
violations. However, most data races do not violate SC. In addition, lock-free data structures …