A survey on high-throughput non-binary LDPC decoders: ASIC, FPGA, and GPU architectures
Non-binary low-density parity-check (NB-LDPC) codes show higher error-correcting
performance than binary low-density parity-check (LDPC) codes when the codeword length …
performance than binary low-density parity-check (LDPC) codes when the codeword length …
A survey and tutorial on contemporary aspects of multiple-valued logic and its application to microelectronic circuits
V Gaudet - IEEE Journal on Emerging and Selected Topics in …, 2016 - ieeexplore.ieee.org
Multiple-valued logic has a history that goes back to the 1920s. Its flagship symposium was
established in 1971. Despite multiple-valued logic's long history, there have been many …
established in 1971. Despite multiple-valued logic's long history, there have been many …
Basic-set trellis min–max decoder architecture for nonbinary ldpc codes with high-order galois fields
Nonbinary low-density parity-check (NB-LDPC) codes outperform their binary counterparts
in terms of error-correction performance. However, the drawback of NB-LDPC decoders is …
in terms of error-correction performance. However, the drawback of NB-LDPC decoders is …
Design space exploration of LDPC decoders using high-level synthesis
Today, high-level synthesis (HLS) tools are being touted as a means to perform rapid
prototyping and shortening the long development cycles needed to produce hardware …
prototyping and shortening the long development cycles needed to produce hardware …
Reduced-complexity nonbinary LDPC decoder for high-order Galois fields based on trellis min–max algorithm
JO Lacruz, F García-Herrero… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
Nonbinary LDPC codes outperform their binary counterparts in different scenarios. However,
they require a considerable increase in complexity, especially in the check-node (CN) …
they require a considerable increase in complexity, especially in the check-node (CN) …
Minimal-set trellis min-max decoder architecture for nonbinary LDPC codes
Nonbinary low-density parity-check (NB-LDPC) codes offer a superior error correction
capability compared to the existing binary counterparts. However, there exist two major …
capability compared to the existing binary counterparts. However, there exist two major …
[PDF][PDF] Robotic controller: ASIC versus FPGA—A review
Reconfigurable technology have been widely researched. This review focused on the
application of using FPGA as a development reconfigurable platform for a controller solution …
application of using FPGA as a development reconfigurable platform for a controller solution …
High-performance NB-LDPC decoder with reduction of message exchange
JO Lacruz, F Garcia-Herrero… - IEEE Transactions on …, 2015 - ieeexplore.ieee.org
This paper presents a novel algorithm based on trellis min-max for decoding non-binary low-
density parity-check (NB-LDPC) codes. This decoder reduces the number of messages …
density parity-check (NB-LDPC) codes. This decoder reduces the number of messages …
Hamming-distance trellis min-max-based architecture for non-binary LDPC decoder
Limitations on hardware resource consumption and throughput make the use of non-binary
low-density parity-check (NB-LDPC) codes challenging in practical applications. This brief …
low-density parity-check (NB-LDPC) codes challenging in practical applications. This brief …
[PDF][PDF] Enabling High-Level Design Strategies for High-Throughput and Low-Power NB-LDPC Decoders
Hardware designers of LDPC decoders used in modern low-power communications are
confronted with the need to perform design space exploration for targeting high throughput …
confronted with the need to perform design space exploration for targeting high throughput …