Design and evaluation of laminated busbar for three-level T-type NPC power electronics building block with enhanced dynamic current sharing

Z Yuan, H Peng, A Deshpande… - IEEE Journal of …, 2019 - ieeexplore.ieee.org
This article focuses on providing the laminated busbar design guidance for a three-level T-
type neutral-pointclamped (3L-TNPC) inverter to achieve low stray inductance and balanced …

Chips classification for suppressing transient current imbalance of parallel-connected silicon carbide MOSFETs

J Ke, Z Zhao, P Sun, H Huang… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
This article addresses the influence of parameters spread on transient current distribution
among parallel-connected silicon carbide (SiC) mosfets and proposes a chips classification …

Device screening strategy for suppressing current imbalance in parallel-connected SiC MOSFETs

B Zhao, Q Yu, P Sun, Y Cai… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Device parameter mismatch generates current imbalance between parallel devices. In
severe cases, the device that withstands excessive current may incur overcurrent failure …

Linear regression model for screening SiC MOSFETs for paralleling to minimize transient current imbalance

J Abuogo, Z Zao, J Ke - IOP Conference Series: Materials …, 2019 - iopscience.iop.org
This paper describes the development of a machine learning model which can be used to
screen SiC MOSFETs for paralleling with minimized transient current imbalance. The spread …

A new screening method for alleviating transient current imbalance of paralleled SiC MOSFETs

Y Liu, X Dai, X Jiang, Z Zeng, F Qi, Y Liu… - 2020 IEEE 1st China …, 2020 - ieeexplore.ieee.org
Due to material defects and immature process technology, the current level of SiC MOSFET
is significantly lower than that of Si IGBT. Connecting multiple chips in parallel has become a …

Analysis and Mitigation on Mismatch-induced Spurious Gate-source Voltages in SiC Bridge-leg Power Modules With Kelvin Sources

C Zhao, L Wang, J Yang, S Wu… - IEEE Journal of …, 2024 - ieeexplore.ieee.org
In bridge-leg configurations, spurious gate-source voltages (crosstalk voltages) can falsely
trigger one switch to turn ON at the complementary switch's turn-ON interval. Previous works …

Closed loop digital design of active gate driver based power converter

M Kumar, Z Feng, S Wang, M Sandell… - 2024 IEEE Applied …, 2024 - ieeexplore.ieee.org
Silicon-Carbide (SiC) MOSFETs have gained significant adoption in power converters due
to their superior performance over their Silicon counterparts. Active gate drivers (AGDs) are …

Overvoltage and Ringing in a State-of-the-art SiC MOSFET Power Module for Traction Inverters

AR Fallico, SA Rizzo, A Raciti… - … of Electrical and …, 2020 - ieeexplore.ieee.org
Research teams from industry and academia have highlighted the advantages obtained
from the introduction of Silicon Carbide (SiC) traction inverter power modules. Similarly …

Influence of parasitic coupling on current sharing in paralleled SiC MOSFET devices

H Zhang, J Ke, J Peng, P Sun, Z Zhao - IET Power Electronics, 2022 - Wiley Online Library
This paper comprehensively investigates the current distribution behaviours of paralleled
SiC MOSFET devices under the parasitic coupling between gate and power loops. Three …

Carrier-based PWM Modulation Method for Evaluation of Multi-Level Inverters

O Solomon - 2022 International Symposium on Power …, 2022 - ieeexplore.ieee.org
This paper describes a simple carrier-based approach for developing and evaluating some
of the key performance characteristics of a multi-level inverters. Three types of carrier-based …