This article presents a fractional-N frequency synthesizer architecture that is able to
overcome the limitations of conventional bang-bang phase-locked loops. A digital …

This article presents a low-voltage (LV) sub-sampling phase-locked loop (LVSSPLL). The
architecture of hybrid dual-path loop-based SSPLL is proposed to mitigate the issue of …

In this work Junctionless (JL) FinFET is designed to operate as an Under Gate (UG)
Dielectric Modulated (DM) biosensor for the detection of various biomolecules-Streptavidin …

This article overviews the design considerations and state-of-the-art of the ring voltage-
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …

A 20-GHz fractional-analog phase-locked loop (PLL) leveraging a novel high-speed charge
pump (CP) and an on-chip frequency reference is demonstrated. An on-chip fully integrable …

Digital integrated circuits have significantly benefited from technology scaling down, while
conventional analog integrated circuits suffer from more design constraints. In recent years …

This letter presents a 56-Gb/s PAM-4 transceiver which achieves a bit error rate of 2× 10-9
through-33 dB of channel insertion loss while consuming 500-mW receiver and 90-mW …

This work presents a low-jitter and low out-of-band noise two-core fractional-digital bang-
bang phase-locked loop (PLL). Two novel techniques are introduced to efficiently suppress …

This paper presents an integer-N bang-bang digital PLL for synthesis of a high purity clock
targeting output frequencies of 12 and 16 GHz using a 500 MHz reference. The PLL uses a …

This paper presents a 14 GHz sub-sampling PLL (SSPLL) with its phase noise analysis for
Ku-band wireless transceivers. The performance enhancement of the phase-locked loop …