This article overviews the design considerations and state-of-the-art of the ring voltage-
controlled oscillator (VCO)-based phase-locked loops (PLLs) for clock generation in different …

This letter proposes a mm-wave fractional-N reference-oversampling (ROS) all-digital phase-
locked loop (ADPLL) for 5G wireless applications utilizing a relatively low but standard …

A 32.768 kHz-reference (REF) phase-locked loop (PLL) can help eliminate the high-
frequency crystal oscillator in a wireless system-on-chip (SoC), which would significantly …

In this article, we propose a digital-to-time conversion technique operating entirely in the
sinusoidal waveform voltage domain of a crystal oscillator (XO) before the signal's final …

Parasitic coupling between the building blocks within a fractional-N phase-locked loop (PLL)
can result in noticeable spurs in its output spectrum, thus affecting the PLL's usability in …

An analog fractional-N phase-locked loop (PLL) is presented, which largely eliminates
quantization noise by overclocking the delta–sigma modulator (DSM). The overclocking …

This article presents a wide-band suppression technique of flicker phase noise (PN) by
means of a gate–drain phase shift in a transformer-based complementary oscillator. We …

A fractional-N frequency synthesizer with low total jitter eg,< 50 fsrms, accounting for both
phase noise (PN) and spurs is essential for enabling the emerging 5G/6G and other high …

This article proposes a mm-wave fractional-N ADPLL employing a reference-waveform
oversampling (ROS) phase detector (PD) that increases its effective rate four times …

In this paper, we prove that rather than the second-order Δ Σ modulator (DSM) as typically
believed using the first-order one yields a faster convergence for the linear-piecewise …