A hypervisor for shared-memory FPGA platforms
Cloud providers widely deploy FPGAs as application-specific accelerators for customer use.
These providers seek to multiplex their FPGAs among customers via virtualization, thereby …
These providers seek to multiplex their FPGAs among customers via virtualization, thereby …
The virtual block interface: A flexible alternative to the conventional virtual memory framework
Computers continue to diversify with respect to system designs, emerging memory
technologies, and application memory demands. Unfortunately, continually adapting the …
technologies, and application memory demands. Unfortunately, continually adapting the …
Software data planes: You can't always spin to win
H Golestani, A Mirhosseini, TF Wenisch - Proceedings of the ACM …, 2019 - dl.acm.org
Today's datacenters demand high-performance, energy-efficient software data planes,
which are widely used in many areas including fast network packet processing, network …
which are widely used in many areas including fast network packet processing, network …
Dylect: Achieving huge-page-like translation performance for hardware-compressed memory
To expand effective memory capacity, hardware memory compression transparently
compresses and packs memory values more densely together in DRAM. This requires …
compresses and packs memory values more densely together in DRAM. This requires …
Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings
K Kanellopoulos, R Bera, K Stojiljkovic… - Proceedings of the 56th …, 2023 - dl.acm.org
Conventional virtual memory (VM) frameworks enable a virtual address to flexibly map to
any physical address. This flexibility necessitates large data structures to store virtual-to …
any physical address. This flexibility necessitates large data structures to store virtual-to …
Compendia: reducing virtual-memory costs via selective densification
S Ainsworth, TM Jones - Proceedings of the 2021 ACM SIGPLAN …, 2021 - dl.acm.org
Virtual-to-physical memory translation is becoming an increasingly dominant cost in
workload execution; as data sizes scale, up to four memory accesses are required per …
workload execution; as data sizes scale, up to four memory accesses are required per …
Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation
As the memory footprint of emerging applications continues to increase, the address
translation becomes a critical performance bottleneck owing to frequent misses on the …
translation becomes a critical performance bottleneck owing to frequent misses on the …
(no) compromis: Paging virtualization is not a fatality
Nested/Extended Page Table (EPT) is the current hardware solution for virtualizing memory
in virtualized systems. It induces a significant performance overhead due to the 2D page …
in virtualized systems. It induces a significant performance overhead due to the 2D page …
rShare: Alleviating long startup on the Cloud-rendering platform through de-systemization
D Tang, M Mao, Y Yao, C Bao, Q Shi, C Xie… - Journal of Systems …, 2023 - Elsevier
WebGL paves the way for the great development of lightweight rendering applications (eg,
web games). However, the target audience of Cloud-rendering frameworks (eg, Google …
web games). However, the target audience of Cloud-rendering frameworks (eg, Google …
DeVAS: Decoupled Virtual Address Spaces
The constant growth of workload size in modern applications is making address translation a
performance bottleneck. In principle, increasing the virtual page size could be …
performance bottleneck. In principle, increasing the virtual page size could be …