A hypervisor for shared-memory FPGA platforms

J Ma, G Zuo, K Loughlin, X Cheng, Y Liu… - Proceedings of the …, 2020 - dl.acm.org
Cloud providers widely deploy FPGAs as application-specific accelerators for customer use.
These providers seek to multiplex their FPGAs among customers via virtualization, thereby …

The virtual block interface: A flexible alternative to the conventional virtual memory framework

N Hajinazar, P Patel, M Patel… - 2020 ACM/IEEE 47th …, 2020 - ieeexplore.ieee.org
Computers continue to diversify with respect to system designs, emerging memory
technologies, and application memory demands. Unfortunately, continually adapting the …

Software data planes: You can't always spin to win

H Golestani, A Mirhosseini, TF Wenisch - Proceedings of the ACM …, 2019 - dl.acm.org
Today's datacenters demand high-performance, energy-efficient software data planes,
which are widely used in many areas including fast network packet processing, network …

Dylect: Achieving huge-page-like translation performance for hardware-compressed memory

G Panwar, M Laghari, E Choukse… - 2024 ACM/IEEE 51st …, 2024 - ieeexplore.ieee.org
To expand effective memory capacity, hardware memory compression transparently
compresses and packs memory values more densely together in DRAM. This requires …

Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings

K Kanellopoulos, R Bera, K Stojiljkovic… - Proceedings of the 56th …, 2023 - dl.acm.org
Conventional virtual memory (VM) frameworks enable a virtual address to flexibly map to
any physical address. This flexibility necessitates large data structures to store virtual-to …

Compendia: reducing virtual-memory costs via selective densification

S Ainsworth, TM Jones - Proceedings of the 2021 ACM SIGPLAN …, 2021 - dl.acm.org
Virtual-to-physical memory translation is becoming an increasingly dominant cost in
workload execution; as data sizes scale, up to four memory accesses are required per …

Pinning Page Structure Entries to Last-Level Cache for Fast Address Translation

O Kwon, Y Lee, S Hong - IEEE Access, 2022 - ieeexplore.ieee.org
As the memory footprint of emerging applications continues to increase, the address
translation becomes a critical performance bottleneck owing to frequent misses on the …

(no) compromis: Paging virtualization is not a fatality

B Teabe, P Yuhala, A Tchana, F Hermenier… - Proceedings of the 17th …, 2021 - dl.acm.org
Nested/Extended Page Table (EPT) is the current hardware solution for virtualizing memory
in virtualized systems. It induces a significant performance overhead due to the 2D page …

rShare: Alleviating long startup on the Cloud-rendering platform through de-systemization

D Tang, M Mao, Y Yao, C Bao, Q Shi, C Xie… - Journal of Systems …, 2023 - Elsevier
WebGL paves the way for the great development of lightweight rendering applications (eg,
web games). However, the target audience of Cloud-rendering frameworks (eg, Google …

DeVAS: Decoupled Virtual Address Spaces

M Mannino, B Peccerillo, A Mondelli… - 2024 IEEE 36th …, 2024 - ieeexplore.ieee.org
The constant growth of workload size in modern applications is making address translation a
performance bottleneck. In principle, increasing the virtual page size could be …