The paper proposes two architectures for a dynamically scalable network-on-chip (NoC) for
dynamically reconfigurable intellectual properties (IPs) to save power. The first architecture …

In an ever-evolving digital world with complex algorithms like machine learning, we need
new strategies for more flexibility to cope with the ever-changing environment. For this …

The communication subsystem of a system-on-chip (SoC) has been an exciting research
area for more than three decades. With benefits ranging from increased power efficiency to …

Network-on-chip (NoC) is a promising communication medium for multi-processor SoCs.
However, the increasing demand of flexible use-cases in SoC applications triggers …

Unlike traditional synchronous design, which has a specific modus operandi, Relative
Timing (RT) design is flexible. This pliability leads to exciting opportunities in engineering …

В работе представлена реализация генерируемой сети на кристалле с различными
параметрами на языке Verilog. Доступные на данный момент топологии: меш, тор и …

Communication between the cores in multi and many-core architectures might be impaired if
they do not employ appropriate interconnection strategies. The use of Networks-on-chip …

В статье представлены Java и HDL модели, являющиеся основой новой гибридной
модели СтнК. Проведено на ее основе моделирование топологий mesh, torus и …