[图书][B] CMOS time-mode circuits and systems: fundamentals and applications

F Yuan - 2018 - books.google.com
Time-mode circuits, where information is represented by time difference between digital
events, offer a viable and technology-friendly means to realize mixed-mode circuits and …

A digitally controlled DC-DC buck converter with automatic digital PFM to PWM transition scheme

N Beohar, D Mandal, V Parasuram… - 2021 IEEE Applied …, 2021 - ieeexplore.ieee.org
An automatic fully-digital pulse frequency modulation (PFM) to pulse width modulation
(PWM) mode transition scheme for digitally controlled DC-DC buck converter is proposed in …

Readout Circuit Design for RRAM Array-Based Computing in Memory Architecture

X Xu, A Wang, Y Shui - Electronics, 2024 - mdpi.com
In recent advancements, the traditional von Neumann architecture has been challenged by
the computational needs of AI. This is due to its high power and data transfer costs. As a …

Design considerations of MASH ΔΣ modulators with GRO-based quantization

M Honarparvar, JM de la Rosa… - … on Circuits and …, 2018 - ieeexplore.ieee.org
A gated ring oscillator (GRO) based multi-stage noise-shaping ΔΣ modulator (ΔΣM) is
presented in this paper. Loop-filter integrators followed by a digitally implemented GRO …

Design techniques for time-mode noise-shaping analog-to-digital converters: a state-of-the-art review

F Yuan - Analog Integrated Circuits and Signal Processing, 2014 - Springer
The paper provides a comprehensive treatment of time-mode noise-shaping analog-to-
digital converters (ADCs). An in-depth examination of the principle, advantages, and …

A scalable high-linearity two-step DTC-assisted voltage–to-time converter with rail-to-rail input-range for time-based circuits

AH Miremadi, O Hashemipour - AEU-International Journal of Electronics …, 2021 - Elsevier
This paper presents a highly digital voltage-to-time converter (VTC), which is compatible
with advances in CMOS scaling and ability of operating under low supply voltages. The …

A 40nm, high bandwidth, VCO-based burst-mode receiver backend for EHF multi-carrier wireless

T Redant, W Dehaene - 2013 IEEE Asian Solid-State Circuits …, 2013 - ieeexplore.ieee.org
A receiver back-end in 40 nm CMOS for an EHF wireless multi-carrier applications is
presented. The system is designed to reduce the bandwidth of a multi-tone I/Q decomposed …

[PDF][PDF] Design and Implementation of an Analog-to-Time-to-Digital converter

JDA van den Broek - … and Computer Science, University of Twente …, 2012 - essay.utwente.nl
This thesis describes the design and implementation of an analog-to-digital converter (ADC)
taking an uncommon two-step approach: a voltage-to-time converter (VTC) converts the …

[图书][B] Architectural Alternatives to Implement High-Performance Delta-Sigma Modulators

M Honarparvar - 2019 - search.proquest.com
The need for hand-held devices, smart-phones and medical implantable microelectronic
systems, is remarkably growing up. However, keeping all these electronic devices power …

Time-Mode Signal Quantization for Use in Sigma-Delta Modulators

M Tamaddon, M Yavari - AUT Journal of Electrical Engineering, 2016 - eej.aut.ac.ir
The rapid scaling in modern CMOS technology has motivated the researchers to design new
analog-to-digital converter (ADC) architectures that can properly work in lower supply …