We present a two-dimensional (2-D) analytical modeling of the surface potential of a double-
gate vertical t-shaped tunnel field-effect transistor (TFET), considering the inherit dual …

The reliability of the CMOS devices is severely affected due to the presence of interface (S
i/S i O 2) trap charges and self-heating effect (SHE). In this paper, we investigated the trap …

The design of CMOS circuits using nanoscale MOSFET has become very difficult nowadays
as device modeling faces new challenges such as short channel effects and mobility …

A novel silicon-on-insulator (SOI)-based tunnel FET (TFET) with two source regions (TSRs)
is proposed and investigated by Sentaurus simulation. The incorporation of the TSR in the …

A subthreshold analytical model for Dual Material Double Gate Junctionless Tunnel FET
(DMDG JLTFET) is developed. To analyze the behavior of short channel device, relevant …

This study presents a gate-all-around InAs–Si vertical tunnel field-effect transistor with a
triple metal gate (VTG-TFET). We obtained improved switching characteristics for the …

In this paper, a novel biomolecule nanocavity immobilization in a dielectric modulated triple-
hybrid metal gate-all-around (THM-GAA) junctionless (JL) NWFET has been proposed to …

In this article, a Ge‐source is employed in split drain Z‐shaped line TFET structure (SD‐ZHP‐
TFET) and named as Ge‐source SD‐ZHP‐TFET. The presence of split drain increases the …

An improved Chimps optimizer algorithm is proposed in this paper and is applied for the
performance optimization of tunnel FET architectures for use in low power VLSI circuits. The …

For the first time, a novel source extension heterojunction gate‐all‐around tunnel FET (SE‐
GAA‐TFET) is proposed and examined using Synopsys TCAD simulator in this manuscript …