[图书][B] Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for Sub-65nm Technology Nodes
BP Wong, A Mittal, GW Starr, F Zach, V Moroz, A Kahng - 2008 - books.google.com
Discover innovative tools that pave the way from circuit and physical design to fabrication
processing Nano-CMOS Design for Manufacturability examines the challenges that design …
processing Nano-CMOS Design for Manufacturability examines the challenges that design …
Yield analysis and optimization
P Gupta, E Papadopoulou - Handbook of Algorithms for Physical …, 2008 - taylorfrancis.com
This chapter discusses yield loss mechanisms, yield analysis and common physical design
methods to improve yield. Yield optimization methods work with the measure, model, and …
methods to improve yield. Yield optimization methods work with the measure, model, and …
Timing yield-aware color reassignment and detailed placement perturbation for bimodal CD distribution in double patterning lithography
Double patterning lithography (DPL) is in current production for memory products, and is
widely viewed as inevitable for logic products at the 32 nm node. DPL decomposes and …
widely viewed as inevitable for logic products at the 32 nm node. DPL decomposes and …
Key directions and a roadmap for electrical design for manufacturability
AB Kahng - ESSCIRC 2007-33rd European Solid-State Circuits …, 2007 - ieeexplore.ieee.org
Semiconductor product value increasingly depends on" equivalent scaling" achieved by
design and design-for-manufacturability (DFM) techniques. This talk addresses trends and a …
design and design-for-manufacturability (DFM) techniques. This talk addresses trends and a …
Timing analysis and optimization implications of bimodal CD distribution in double patterning lithography
Double patterning lithography (DPL) is in current production for memory products, and is
widely viewed as inevitable for logic products at the 32 nm node. DPL decomposes and …
widely viewed as inevitable for logic products at the 32 nm node. DPL decomposes and …
Manufacturability aware routing in nanometer VLSI
This monograph surveys key research challenges and recent results of manufacturability
aware routing in nanometer VLSI designs. The manufacturing challenges have their root …
aware routing in nanometer VLSI designs. The manufacturing challenges have their root …
Computer-aided design for low-power robust computing in nanoscale CMOS
D Sylvester, A Srivastava - Proceedings of the IEEE, 2007 - ieeexplore.ieee.org
This work argues that the foremost challenges to the continued rapid improvements in
CMOS integrated circuit (IC) performance are power consumption and design robustness …
CMOS integrated circuit (IC) performance are power consumption and design robustness …
Timing yield-aware color reassignment and detailed placement perturbation for double patterning lithography
Double patterning lithography (DPL) is a likely resolution enhancement technique for IC
production in 32 nm and below technology nodes. However, DPL gives rise to two …
production in 32 nm and below technology nodes. However, DPL gives rise to two …
Manufacturability-aware design of standard cells
H Muta, H Onodera - IEICE transactions on fundamentals of …, 2007 - search.ieice.org
We focus our attention on the layout dependent Across Chip Linewidth Variability (ACLV) of
gate-forming poly-silicon patterns as a measure for manufacturability, which is a major …
gate-forming poly-silicon patterns as a measure for manufacturability, which is a major …
Parametric dfm solution for analog circuits: electrical-driven hotspot detection, analysis, and correction flow
H Eissa, RF Salem, A Arafa, S Hany… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
As VLSI technology pushes into advanced nodes, designers and foundries have exposed a
hitherto insignificant set of yield problems. To combat yield failures, the semiconductor …
hitherto insignificant set of yield problems. To combat yield failures, the semiconductor …