Memory systems are becoming bandwidth constrained and data compression is seen as a
simple technique to increase their effective bandwidth. However, data compressionrequires …

Recent work in FPGA-accelerated simulation of ASICs has shown that much of a simulator
can be automatically generated from ASIC RTL. Alas, these works rely on simple models of …

Compression is seen as a simple technique to increase the effective cache capacity.
Unfortunately, compression techniques either incur tag area overheads or restrict cache …

Data movement over long and highly capacitive interconnects is responsible for a large
fraction of the energy consumed in nanometer ICs. DDRx, the most broadly adopted family …

The community accepted the need for a detailed simulation of main memory. Currently, the
CPU simulators are usually coupled with the cycle-accurate main memory simulators …

The simulation of Dynamic Random Access Memories (DRAMs) in a system context requires
highly accurate models due to the complex timing and power behavior of DRAMs. However …

During the last few years, computer performance has reached a turning point where
computing power is no longer the only important concern. This way, the emphasis is shifting …

This paper introduces a new memory scheduling policy called LAMS, which is inspired by a
recently proposed memory architecture and targets for future high capacity memory systems …

Spin-Transfer Torque Random Access Memory (STT-RAM) is a potential alternative for
SRAM-based on-chip caches. STT-RAM offers high density and low leakage power, thereby …

In recent years, an increasing number of different JEDEC memory standards, like DDR4/5,
LPDDR4/5, GDDR6, Wide I/O2, HBM2, and NVDIMM-P have been specified, which differ …