Spin-transfer torque memories: Devices, circuits, and systems
Spin-transfer torque magnetic memory (STT-MRAM) has gained significant research interest
due to its nonvolatility and zero standby leakage, near unlimited endurance, excellent …
due to its nonvolatility and zero standby leakage, near unlimited endurance, excellent …
Stash: Have your scratchpad and cache it too
Heterogeneous systems employ specialization for energy efficiency. Since data movement
is expected to be a dominant consumer of energy, these systems employ specialized …
is expected to be a dominant consumer of energy, these systems employ specialized …
Dynamically reconfigurable hybrid cache: An energy-efficient last-level cache design
The recent development of non-volatile memory (NVM), such as spin-torque transfer
magnetoresistive RAM (STT-RAM) and phase-change RAM (PRAM), with the advantage of …
magnetoresistive RAM (STT-RAM) and phase-change RAM (PRAM), with the advantage of …
A case for richer cross-layer abstractions: Bridging the semantic gap with expressive memory
N Vijaykumar, A Jain, D Majumdar… - 2018 ACM/IEEE 45th …, 2018 - ieeexplore.ieee.org
This paper makes a case for a new cross-layer interface, Expressive Memory (XMem), to
communicate higher-level program semantics from the application to the system software …
communicate higher-level program semantics from the application to the system software …
Impact of cache architecture and interface on performance and area of FPGA-based processor/parallel-accelerator systems
We describe new multi-ported cache designs suitable for use in FPGA-based
processor/parallel-accelerator systems, and evaluate their impact on application …
processor/parallel-accelerator systems, and evaluate their impact on application …
Cache design with domain wall memory
R Venkatesan, VJ Kozhikkottu… - IEEE Transactions …, 2015 - ieeexplore.ieee.org
Domain wall memory (DWM) is a recently developed spin-based memory technology in
which several bits of data are densely packed into the domains of a ferromagnetic wire …
which several bits of data are densely packed into the domains of a ferromagnetic wire …
A heuristic ant algorithm for solving QoS multicast routing problem
In this paper, we present an ant colony-based heuristic to solve QoS (quality of service)
constrained multicast routing problems. Our algorithm considers multiple QoS metrics, such …
constrained multicast routing problems. Our algorithm considers multiple QoS metrics, such …
High-endurance hybrid cache design in CMP architecture with cache partitioning and access-aware policies
C Lin, JN Chiou - IEEE Transactions on Very Large Scale …, 2014 - ieeexplore.ieee.org
In recent years, nonvolatile memory (NVM) technologies, such as spin-transfer torque
random-access memory (RAM)(STT-RAM) and phase change RAM, have drawn a lot of …
random-access memory (RAM)(STT-RAM) and phase change RAM, have drawn a lot of …
Static and dynamic co-optimizations for blocks mapping in hybrid caches
In this paper, a combined static and dynamic scheme is proposed to optimize the block
placement for endurance and energy-efficiency in a hybrid SRAM and STT-RAM cache. With …
placement for endurance and energy-efficiency in a hybrid SRAM and STT-RAM cache. With …
[PDF][PDF] Toward cache-friendly hardware accelerators
Increasing demand for power-efficient, high-performance computing has spurred a growing
number and diversity of hardware accelerators in mobile Systems on Chip (SoCs) as well as …
number and diversity of hardware accelerators in mobile Systems on Chip (SoCs) as well as …