A review of hot carrier degradation in n-channel MOSFETs—Part I: Physical mechanism
S Mahapatra, U Sharma - IEEE Transactions on Electron …, 2020 - ieeexplore.ieee.org
Transistor parametric drift due to conductionmode hot carrier degradation (HCD) in n-
MOSFETs is reviewed, for longand short-channel length (LCH) devices having different …
MOSFETs is reviewed, for longand short-channel length (LCH) devices having different …
A device-to-system perspective regarding self-heating enhanced hot carrier degradation in modern field-effect transistors: A topical review
As foreseen by Keyes in the late 1960s, the self-heating effect has emerged as an important
concern for device performance, output power density, run-time variability, and reliability of …
concern for device performance, output power density, run-time variability, and reliability of …
Understanding the suppressed charge trapping in relaxed- and strained-Ge/SiO2/HfO2 pMOSFETs and implications for the screening of alternative high-mobility …
We study charge trapping in a variety of Ge-based pMOS and nMOS technologies, either
with Si passivation and conventional SiO 2/HfO 2 gate stack, or with GeO x/high-k gate …
with Si passivation and conventional SiO 2/HfO 2 gate stack, or with GeO x/high-k gate …
A review of hot carrier degradation in n-channel MOSFETs—Part II: Technology scaling
S Mahapatra, U Sharma - IEEE Transactions on Electron …, 2020 - ieeexplore.ieee.org
Transistor parametric drift due to conduction mode hot carrier degradation (HCD) is
reviewed. The time kinetics in n-channel MOSFETs and FinFETs is analyzed for channel …
reviewed. The time kinetics in n-channel MOSFETs and FinFETs is analyzed for channel …
Analysis of hcd effects for nmos transistor with technology scaling
Hot carrier degradation (HCD) is a significant cause of concern regarding the reliability
issues for metal oxide semiconductor field effect transistors (MOSFETs) in the nanoscale …
issues for metal oxide semiconductor field effect transistors (MOSFETs) in the nanoscale …
3D modeling of spatio-temporal heat-transport in III-V gate-all-around transistors allows accurate estimation and optimization of nanowire temperature
Excellent electrostatic control offered by gate-all-around (GAA) geometry makes
multinanowire (multi-NW) MOSFET a promising candidate for sub-10-nm technology nodes …
multinanowire (multi-NW) MOSFET a promising candidate for sub-10-nm technology nodes …
Modeling of hot-carrier degradation in nLDMOS devices: Different approaches to the solution of the Boltzmann transport equation
P Sharma, S Tyaginov, Y Wimmer… - … on Electron Devices, 2015 - ieeexplore.ieee.org
We propose two different approaches to describe carrier transport in n-laterally diffused
MOS (nLDMOS) transistor and use the calculated carrier energy distribution as an input for …
MOS (nLDMOS) transistor and use the calculated carrier energy distribution as an input for …
On the universality of hot carrier degradation: Multiple probes, various operating regimes, and different MOSFET architectures
S Mahapatra, R Saikia - IEEE Transactions on Electron …, 2018 - ieeexplore.ieee.org
Comprehensive review and reanalysis are done on previously reported experimental hot
carrier degradation data in various MOSFET architectures. The universality of time kinetics …
carrier degradation data in various MOSFET architectures. The universality of time kinetics …
Characterization and modeling of electrical stress degradation in STI-based integrated power devices
Lateral DMOS transistors are widely used in mixed-signal integrated-circuit design as
integrated high-voltage switches and drivers. The LDMOS with shallow-trench isolation (STI) …
integrated high-voltage switches and drivers. The LDMOS with shallow-trench isolation (STI) …
A SPICE compatible compact model for hot-carrier degradation in MOSFETs under different experimental conditions
U Sharma, S Mahapatra - IEEE Transactions on Electron …, 2018 - ieeexplore.ieee.org
A compact hot-carrier degradation (HCD) time kinetics model is proposed for conventional,
lightly doped drain, and drain extended MOSFETs and FinFETs. It can predict measured …
lightly doped drain, and drain extended MOSFETs and FinFETs. It can predict measured …