A PLL clock generator with 5 to 110 MHz of lock range for microprocessors
IA Young, JK Greason, KL Wong - IEEE Journal of Solid-State …, 1992 - ieeexplore.ieee.org
A microprocessor clock generator based on an analog phase-locked loop (PLL) is described
for deskewing the internal logic control lock to an external system lock. This PLL is fully …
for deskewing the internal logic control lock to an external system lock. This PLL is fully …
Versatile insensitive current-mode universal biquad implementation using current conveyors
HY Wang, CT Lee - IEEE Transactions on Circuits and Systems …, 2001 - ieeexplore.ieee.org
We present a versatile multi-input-multi-output biquad configuration. Either a three-input
single-output or a single-input three-output universal filter can be realized. The proposed …
single-output or a single-input three-output universal filter can be realized. The proposed …
CFOA-based first-order voltage-mode universal filters
In this paper, two new CFOA-based first-order voltage-mode universal filters are proposed.
Both of the filters use an additional unity gain-inverting amplifier. The first proposed filter …
Both of the filters use an additional unity gain-inverting amplifier. The first proposed filter …
A novel CMOS current conveyor realization with an electronically tunable current mode filter suitable for VLSI
HO Elwan, AM Soliman - … on Circuits and Systems II: Analog …, 1996 - ieeexplore.ieee.org
A novel CMOS realization of the second generation current conveyor is given. A circuit
which compensates the voltage offset due to channel length modulation effect is then …
which compensates the voltage offset due to channel length modulation effect is then …
Supplementary DDCC+ based universal filter with grounded passive elements
A new voltage-mode (VM) analog filter is proposed in this paper. The proposed circuit is
composed of three plus-type single output DDCCs and only grounded passive elements that …
composed of three plus-type single output DDCCs and only grounded passive elements that …
A new active device namely S-CCI and its applications: Simulated floating inductor and quadrature oscillators
A new active building block namely, subtractor connected first-generation current conveyor
(S-CCI) is introduced in this paper. A simulated floating inductor (SFI) and two new …
(S-CCI) is introduced in this paper. A simulated floating inductor (SFI) and two new …
Extended exploration grey wolf optimization, CFOA-based circuit implementation of the sigr function and its applications in finite-time terminal sliding mode control
The development of closed-loop circuit realizations of chaotic synchronization and control is
considered a promising aspect of analog electronics. Therefore, this paper explores the use …
considered a promising aspect of analog electronics. Therefore, this paper explores the use …
A new electronically fine tunable grounded voltage controlled positive resistor
A new grounded voltage controlled positive resistor (GVCPR) is proposed in this brief. The
proposed GVCPR with a single control voltage is composed of only six MOS transistors …
proposed GVCPR with a single control voltage is composed of only six MOS transistors …
VLSI implementation of synaptic weighting and summing in pulse coded neural-type cells
G Moon, ME Zaghloul… - IEEE Transactions on …, 1992 - ieeexplore.ieee.org
Presents the hardware realization for synaptic weighting and summing using pulse-coded
neural-type cells (NTCs). The basic information processing element (NTC) encodes the …
neural-type cells (NTCs). The basic information processing element (NTC) encodes the …
A simple configuration for realizing voltage-controlled impedances
R Senani, DR Bhaskar - … Transactions on Circuits and Systems I …, 1992 - ieeexplore.ieee.org
A simple configuration is proposed that incorporates an effective cancellation of the
nonlinearity of the V/sub DS/-i/sub D/characteristics of the FET to produce a voltage …
nonlinearity of the V/sub DS/-i/sub D/characteristics of the FET to produce a voltage …