Pushing the level of abstraction of digital system design: A survey on how to program fpgas
Field Programmable Gate Arrays (FPGAs) are spatial architectures with a heterogeneous
reconfigurable fabric. They are state-of-the-art for prototyping, telecommunications …
reconfigurable fabric. They are state-of-the-art for prototyping, telecommunications …
Fpga acceleration for big data analytics: Challenges and opportunities
J Hoozemans, J Peltenburg… - IEEE Circuits and …, 2021 - ieeexplore.ieee.org
The big data revolution has ushered an era with ever increasing volumes and complexity of
data requiring ever faster computational analysis. During this very same era, CPU …
data requiring ever faster computational analysis. During this very same era, CPU …
Type-directed scheduling of streaming accelerators
Designing efficient, application-specialized hardware accelerators requires assessing trade-
offs between a hardware module's performance and resource requirements. To facilitate …
offs between a hardware module's performance and resource requirements. To facilitate …
Bind the gap: Compiling real software to hardware FFT accelerators
Specialized hardware accelerators continue to be a source of performance improvement.
However, such specialization comes at a programming price. The fundamental issue is that …
However, such specialization comes at a programming price. The fundamental issue is that …
AnyHLS: High-level synthesis with partial evaluation
Field programmable gate arrays (FPGAs) excel in low power and high throughput
computations, but they are challenging to program. Traditionally, developers rely on …
computations, but they are challenging to program. Traditionally, developers rely on …
Let Coarse-Grained Resources Be Shared: Mapping Entire Neural Networks on FPGAs
Traditional High-Level Synthesis (HLS) provides rapid prototyping of hardware accelerators
without coding with Hardware Description Languages (HDLs). However, such an approach …
without coding with Hardware Description Languages (HDLs). However, such an approach …
ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators
S Han, M Jang, J Kang - Proceedings of the 28th ACM International …, 2023 - dl.acm.org
Functional programming's benefits for hardware description have long been recognized in
the literature. In particular, functional hardware description languages provide combinators …
the literature. In particular, functional hardware description languages provide combinators …
FLOWER: A comprehensive dataflow compiler for high-level synthesis
FPGAs have found their way into data centers as accelerator cards, making reconfigurable
computing more accessible for high-performance applications. At the same time, new high …
computing more accessible for high-performance applications. At the same time, new high …
Optimizing data reshaping operations in functional IRs for high-level synthesis
FPGAs (Field Programmable Gate Arrays) have become the substrate of choice to
implement accelerators. They deliver high performance with low power consumption, while …
implement accelerators. They deliver high performance with low power consumption, while …
Modular Hardware Design of Pipelined Circuits with Hazards
M Jang, J Rhee, W Lee, S Zhao, J Kang - Proceedings of the ACM on …, 2024 - dl.acm.org
Modular design is critical in reducing hardware designer's cognitive load and development
cost. However, it is challenging to modularize high-performance pipelined circuits with …
cost. However, it is challenging to modularize high-performance pipelined circuits with …