Pushing the level of abstraction of digital system design: A survey on how to program fpgas

ED Sozzo, D Conficconi, A Zeni, M Salaris… - ACM Computing …, 2022 - dl.acm.org
Field Programmable Gate Arrays (FPGAs) are spatial architectures with a heterogeneous
reconfigurable fabric. They are state-of-the-art for prototyping, telecommunications …

Fpga acceleration for big data analytics: Challenges and opportunities

J Hoozemans, J Peltenburg… - IEEE Circuits and …, 2021 - ieeexplore.ieee.org
The big data revolution has ushered an era with ever increasing volumes and complexity of
data requiring ever faster computational analysis. During this very same era, CPU …

Type-directed scheduling of streaming accelerators

D Durst, M Feldman, D Huff, D Akeley, R Daly… - Proceedings of the 41st …, 2020 - dl.acm.org
Designing efficient, application-specialized hardware accelerators requires assessing trade-
offs between a hardware module's performance and resource requirements. To facilitate …

Bind the gap: Compiling real software to hardware FFT accelerators

J Woodruff, J Armengol-Estapé, S Ainsworth… - Proceedings of the 43rd …, 2022 - dl.acm.org
Specialized hardware accelerators continue to be a source of performance improvement.
However, such specialization comes at a programming price. The fundamental issue is that …

AnyHLS: High-level synthesis with partial evaluation

MA Özkan, A Pérard-Gayot, R Membarth… - … on Computer-Aided …, 2020 - ieeexplore.ieee.org
Field programmable gate arrays (FPGAs) excel in low power and high throughput
computations, but they are challenging to program. Traditionally, developers rely on …

Let Coarse-Grained Resources Be Shared: Mapping Entire Neural Networks on FPGAs

TH Juang, C Schlaak, C Dubach - ACM Transactions on Embedded …, 2023 - dl.acm.org
Traditional High-Level Synthesis (HLS) provides rapid prototyping of hardware accelerators
without coding with Hardware Description Languages (HDLs). However, such an approach …

ShakeFlow: Functional Hardware Description with Latency-Insensitive Interface Combinators

S Han, M Jang, J Kang - Proceedings of the 28th ACM International …, 2023 - dl.acm.org
Functional programming's benefits for hardware description have long been recognized in
the literature. In particular, functional hardware description languages provide combinators …

FLOWER: A comprehensive dataflow compiler for high-level synthesis

P Amiri, A Pérard-Gayot, R Membarth… - … Conference on Field …, 2021 - ieeexplore.ieee.org
FPGAs have found their way into data centers as accelerator cards, making reconfigurable
computing more accessible for high-performance applications. At the same time, new high …

Optimizing data reshaping operations in functional IRs for high-level synthesis

C Schlaak, TH Juang, C Dubach - … of the 23rd ACM SIGPLAN/SIGBED …, 2022 - dl.acm.org
FPGAs (Field Programmable Gate Arrays) have become the substrate of choice to
implement accelerators. They deliver high performance with low power consumption, while …

Modular Hardware Design of Pipelined Circuits with Hazards

M Jang, J Rhee, W Lee, S Zhao, J Kang - Proceedings of the ACM on …, 2024 - dl.acm.org
Modular design is critical in reducing hardware designer's cognitive load and development
cost. However, it is challenging to modularize high-performance pipelined circuits with …