Apparatus and method of early pixel discarding in graphic processing unit
SJ Son, SY Jung, CM Park, KJ Min, SO Woo - US Patent 8,624,894, 2014 - Google Patents
(57) ABSTRACT A method to discard pixels early includes a first early depth test maintaining
a depth value on a pixel to be discarded by a discard instruction, and a second early depth …
a depth value on a pixel to be discarded by a discard instruction, and a second early depth …
An SoC with 1.3 Gtexels/s 3-D graphics full pipeline for consumer applications
A high-speed three-dimensional (3-D) graphics SoC for consumer applications is presented.
A 166-MHz 3-D graphics full pipeline engine with performance of 33 Mvertices/s and 1.3 …
A 166-MHz 3-D graphics full pipeline engine with performance of 33 Mvertices/s and 1.3 …
Tiled prefetched and cached depth buffer
MH Anderson, DM Chuang, G Shippee… - US Patent …, 2012 - Google Patents
6,008,820 A* 12/1999 Chauvin et al................ 34.5/5O2 6,115,047 A* 9/2000
Deering........................ 345,422 predictive, using triangle geometry information from previ ous …
Deering........................ 345,422 predictive, using triangle geometry information from previ ous …
Series–parallel pipeline architecture for high-resolution catadioptric panoramic unwrapping
LD Chen, MJ Zhang, ZH Xiong - IET image processing, 2010 - IET
To implement high-speed panoramic unwrapping of high-resolution catadioptric
omnidirectional images on field-programmable gate array (FPGA), a novel design technique …
omnidirectional images on field-programmable gate array (FPGA), a novel design technique …
Area-efficient pixel rasterization and texture coordinate interpolation
D Kim, LS Kim - Computers & Graphics, 2008 - Elsevier
In this paper, new pixel rasterization and texture coordinate interpolation algorithms are
presented to reduce silicon area. The proposed pixel rasterization based on the …
presented to reduce silicon area. The proposed pixel rasterization based on the …
A pixel cache architecture with selective placement scheme based on z-test result
KW Lee, WC Park, IS Kim, TD Han - Microprocessors and Microsystems, 2005 - Elsevier
Recently, most 3D graphics rendering processors include a pixel cache storing z-data and
color data to reduce the memory latency and bandwidth requirement. In this paper, we …
color data to reduce the memory latency and bandwidth requirement. In this paper, we …
An effective visibility culling method based on cache block
MH Choi, WC Park, F Neelamkavil… - IEEE Transactions on …, 2006 - ieeexplore.ieee.org
As the complexity of 3D scenes is on the increase, the search for an effective visibility culling
method has become one of the most important issues to be addressed in the design of 3D …
method has become one of the most important issues to be addressed in the design of 3D …
Simulation and development environment for mobile 3D graphics architectures
This paper describes a simulation and development environment for designing mobile three-
dimensional (3D) graphics architectures. The proposed simulation and verification …
dimensional (3D) graphics architectures. The proposed simulation and verification …
A low-power implementation of 3d graphics system for embedded mobile systems
C Park, H Kim, J Kim - 2006 IEEE/ACM/IFIP Workshop on …, 2006 - ieeexplore.ieee.org
For mobile 3D graphics systems, even though performance requirements are met, an
efficient power management is even more important for battery-powered mobile devices …
efficient power management is even more important for battery-powered mobile devices …
An Area Efficient Early -Test Method for 3-D Graphics Rendering Hardware
In this paper, we propose a new early z-test which requires a minimized internal memory
while removing redundant z and color reads as well as texture reads. The proposed method …
while removing redundant z and color reads as well as texture reads. The proposed method …