Evaluating forksheet FET reliability concerns by experimental comparison with co-integrated nanosheets
A novel forksheet (FSH) FET architecture has been proposed earlier, consisting of vertically
stacked n-and p-type sheets at opposing sides of a dielectric wall, particularly beneficial for …
stacked n-and p-type sheets at opposing sides of a dielectric wall, particularly beneficial for …
Negative bias-temperature instabilities and low-frequency noise in Ge FinFETs
Negative bias-temperature instabilities and low-frequency noise are investigated in strained
Ge MOS FinFETs with SiO textsubscript 2/HfO textsubscript 2 gate dielectrics. The extracted …
Ge MOS FinFETs with SiO textsubscript 2/HfO textsubscript 2 gate dielectrics. The extracted …
Understanding and modeling opposite impacts of self-heating on hot-carrier degradation in n-and p-channel transistors
We extend our framework for hot-carrier degradation (HCD) modeling by covering the
impact of self-heating (SH) on HCD. This impact is threefold:(i) perturbation of carrier …
impact of self-heating (SH) on HCD. This impact is threefold:(i) perturbation of carrier …
Interactive Lattice and Process-Stress Responses in the Sub-7 nm Germanium-Based Three-Dimensional Transistor Architecture of FinFET and Nanowire GAAFET
CC Lee, PC Huang, TP Hsiang - IEEE Transactions on Electron …, 2022 - ieeexplore.ieee.org
The comprehensive layout-dependence lattice and process-stress variations and induced
mobility gain in sub-7 nm germanium (Ge)-based Fin-type field-effect transistors (FinFETs) …
mobility gain in sub-7 nm germanium (Ge)-based Fin-type field-effect transistors (FinFETs) …
The impact of self-heating and its implications on hot-carrier degradation–A modeling study
A combination of hot-carrier degradation (HCD) and self-heating (SH) was acknowledged to
be the most detrimental reliability issue in ultra-scaled field-effect-transistors (FETs) with …
be the most detrimental reliability issue in ultra-scaled field-effect-transistors (FETs) with …
Negative-bias-stress and total-ionizing-dose effects in deeply scaled Ge-GAA nanowire pFETs
Negative-bias-stress and total-ionizing-dose (TID) effects in deeply scaled Ge-gate-all-
around (GAA) nanowire (NW) devices are characterized for different biasing conditions …
around (GAA) nanowire (NW) devices are characterized for different biasing conditions …
Observation of mobility and velocity behaviors in ultra-scaled LG= 15 nm silicon nanowire field-effect transistors with different channel diameters
Experimentally, two critical device performance factors, apparent mobility (μ app) and virtual
source velocity (v x0) were investigated down to effective channel length (L eff)= 15 nm …
source velocity (v x0) were investigated down to effective channel length (L eff)= 15 nm …
Reliability challenges in Forksheet Devices
E Bury, M Vandemaele, J Franco… - 2023 IEEE …, 2023 - ieeexplore.ieee.org
The forksheet (FSH) device architecture is a possible candidate towards continued logic cell
downscaling. It consists of vertically stacked n-and p-type sheets at opposing sides of a …
downscaling. It consists of vertically stacked n-and p-type sheets at opposing sides of a …
Physical modeling the impact of self-heating on hot-carrier degradation in pNWFETs
We develop and validate a physics-based modeling framework for coupled hot-carrier
degradation (HCD) and self-heating (SH). Within this framework, we obtain the lattice …
degradation (HCD) and self-heating (SH). Within this framework, we obtain the lattice …
A Comparative Study of AC Positive Bias Temperature Instability of Germanium nMOSFETs With GeO₂/Ge and Si-cap/Ge Gate Stack
R Gao, J Ma, X Lin, X Zhang, Y En, G Lu… - IEEE Journal of the …, 2021 - ieeexplore.ieee.org
AC positive bias temperature instability (PBTI) of germanium nMOSFETs with GeO 2/Ge and
Si-cap/Ge gate stack was investigated in this brief. AC-DC-AC alternating PBTI stress tests …
Si-cap/Ge gate stack was investigated in this brief. AC-DC-AC alternating PBTI stress tests …