We present a novel reconfigurable hardware architecture for interpolation filtering in high
efficient video coding that adapts to run-time changes of the number of interpolation filter …

An energy-efficient hybrid on-chip video memory architecture (enHyV) is presented that
combines private and shared memories using a hybrid design (ie, SRAM and emerging STT …

An energy-efficient distributed Scratchpad Video Memory Architecture (dSVM) for the next-
generation parallel High Efficiency Video Coding is presented. Our dSVM combines private …

An adaptive power management of on-chip video memory for Multiview Video Coding is
presented. It leverages texture, motion and disparity properties of objects and their …

A low-power architecture for an on-chip multi-banked video memory for motion and disparity
estimation in Multiview Video Coding is proposed. The memory organization (size, banks …

Power management for Kilo-core processors have become an intricate problem due to the
scalability issues and mixed-workloads of massively multi-threaded applications. This paper …

One of the most concerning issues in current video coding systems relies on the bottleneck
caused by the intense external memory access required by motion estimation. As memory …

Hybrid video standards rely on encoding prediction residues. To improve coding efficiency
of inter-frame prediction, interpolated samples may be generated in fractional positions ie …

This paper presents a hardware design for the Fractional Motion Estimation (FME) of the
High Efficiency Video Coding (HEVC) standard. The solution designed in this work uses a …

In this work we present a framework that profiles HEVC (High Efficiency Video Coding)
encoders modules focusing on cache memory performance and energy. This framework …