Butterfly pitch-angle distributions observed by ISEE-1

TA Fritz, M Alothman, J Bhattacharjya… - Planetary and Space …, 2003 - Elsevier
The ISEE-1 satellite has observed butterfly pitch-angle distributions (PAD) in protons and
electrons from 20 keV to 2 MeV in the low latitude outer magnetosphere, which showed a …

A routing aggregation for load balancing network-on-chip

X Zhou, L Liu, Z Zhu, D Zhou - Journal of Circuits, Systems and …, 2015 - World Scientific
A routing aggregation (RA) is proposed for load balancing network-on-chip (NoC). The
computing nodes with dense traffic and long distance in network are gathered into the same …

Pareto-optimal cost optimization for large scale cloud systems using joint allocation of resources

S Mishra, AK Sangaiah, MN Sahoo… - Journal of Ambient …, 2023 - Springer
Optimal resource allocation in cloud systems is NP-hard due to the involvement of several
conflicting objectives and unpredictable cloud traffic. To improve user satisfaction and …

[HTML][HTML] Design and reliability analysis of a novel redundancy topology architecture

F Li, W Liu, W Gao, Y Liu, Y Hu - Sensors, 2022 - mdpi.com
Topology architecture has a decisive influence on network reliability. In this paper, we
design a novel redundancy topology and analyze the structural robustness, the number of …

A Novel Hybrid Hexagonal Star Topology for On-Chip Interconnection Networks

V Lakshmi Kiranmai… - Journal of Circuits, Systems …, 2023 - World Scientific
Network-on-Chip (NoC) is an emerging and efficient on-chip interconnection network. NoC
is expected to be the communication backbone of next-generation Multi-processor System …

Implementing a partial group based routing for homogeneous fat tree network on chip architecture

A Biswas, HJ Mahanta… - 2014 IEEE International …, 2014 - ieeexplore.ieee.org
As the growing consumer electronic market imposes constraint such as compact product
design and strict time to market, the traditional method of chip designing failed miserably to …

Performance evaluation of modern network-on-chip router architectures

J Latif, S Azam, HN Chaudhry… - International Journal of …, 2016 - journal.uob.edu.bh
On chip interconnection networks simplify the challenges of integrating large number of
processing elements. Routers are backbone of networks. Buffers and crossbar in router …

Design trade off and performance analysis of router architectures in network-on-chip

J Latif, HN Chaudhry, S Azam - Procedia Computer Science, 2015 - Elsevier
On chip interconnection networks simplify the challenges of integrating large number of
processing elements. Routers are backbone of networks. Buffers and crossbar in router …

[HTML][HTML] Design and Analysis of a New Reduced Switch Scalable MIN Fat-Tree Topology

A Biswas, A Hussain - Computación y Sistemas, 2022 - scielo.org.mx
This paper presents a reduced switch scalable MIN Fat-Tree with new inter-router
connections. Unlike the conventional Fat-Tree, consecutive switches are connected with …

A fully grouped routing for Homogeneous FAT Tree Network—On—Chip topology

A Biswas, MA Hussain - 2016 International Conference on …, 2016 - ieeexplore.ieee.org
A routing algorithm plays a critical role in the performance of a Network-on-Chip
architecture. An apt routing strategy should cater the performance demands expected from …