The primary focus of this paper is to discuss the modeling of jitter caused by power supply
noise (PSN), named power supply induced jitter (PSIJ). A holistic discussion is presented …

An efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed
designs is presented. Semianalytical expressions for jitter are derived based on separating …

This paper presents an efficient method to estimate jitter in a chain of CMOS inverters in the
presence of multiple noise sources, including the power supply noise, input data noise, and …

This article presents an analytical approach to determine jitter for a CMOS inverter in the
presence of power supply noise (PSN). The deviation in the transition edge of the output …

This paper demonstrates a very simple and highly accurate expression of power supply-
induced jitter sensitivity transfer function for CMOS buffer chain. The transfer function is …

Precise analytical models of power supply noise induced jitter (PSIJ) at inverter chains are
proposed. Based on the piecewise linear approximated IV curve model, analytical models of …

The transfer functions relating supply voltage fluctuations to jitter are analytically derived in
closed form expressions for a single-ended buffer. The analytic transfer functions are …

Supply fluctuation is one of the most significant factors that cause jitter in high-speed I/O
links. The traditional SPICE simulation or measuring method for power supply induced jitter …

In this work, a generalized power supply induced jitter (PSIJ) model is proposed. The PSIJ
sensitivity is obtained based on the evaluation of driver power supply rejection ratio (PSRR) …

An analytical model of power supply noise induced jitter (PSIJ) at inverter chains is
proposed. Based on the piecewise linear approximated IV curve model, closed-form …