Cell placement is such a critical step for chip physical design that it needs many kinds of
efforts for improvement. Recently, designs with 2D processing element arrays have become …

The remarkable breakthroughs in deep learning have led to a dramatic thirst for
computational resources to tackle interesting real-world problems. Various neural network …

This work proposes a novel latch placement methodology by computing optimized
placement templates with significantly lower local clock tree capacitance at a one-time cost …

This article presents an analytical-based placement algorithm to handle dataflow constraint
for mixed-size circuits. To quickly obtain a better placement at an early stage, engineers …

Abstract Modern Electronic Design Automation (EDA) is complex and computationally
challenging. It consists of a series of difficult optimization problems, accompanied by various …

Placement is a fundamental optimization step to compute cell locations. The quality of
results in Clock Tree Synthesis (CTS) and routing stages is impacted by the placement …

We propose a new coarse-grained structural placement methodology tightly coupled with
logic synthesis to exploit inherent structure of a synthesized parallel multiplier. The proposed …

Datapath macros are essential components of integrated circuits. The high regularity of
datapaths allows compact layout design during placement. In some cases, datapath macros …

Data path circuits are regular and best placed in bit-sliced pattern for improved Quality of
Results such as timing, power, congestion and area. The cells in a column of bit slice …

Regular structures, like datapath, are important components of integrated circuits. Datapath
logic is usually placed with high regularity and compactness for higher performance by …